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Visitor maxlutece
Visitor
12,954 Views
Registered: ‎07-30-2014

Atlys DDR2 memory

Hi !


I'm currently working on a project on FPGA. So I try to store a matrix into the DDR2 memory of my Atlys board but I've encountered problems ...


For the beginning I wrote a program on Xilinx which store 20 data of 32 bits in the memory and after that I tried to read the memory value of those cases on the LED. At each button push I display the next value but the problem is I don't have all the values.


More in details, I used a MIG core for interfacing the memory.The memory part reference is EDE1116AXXX-8E is set at the frequency 333.33 MHz.


The datasheet is available here http://www.xilinx.com/support/documentation/user_guides/ug388.pdf


I think that the problem can result about clocks :


- c3_sysclk_2x and c3_sysclk_2x_180 set to 666.66 Mhz
-calibration clock c3_mcb_drp_clk is set to 83 MHz (should be between 50 and 100 MHz)
-user clock c3_clk0 that is used for command writing and reading is set 333.33 MHz


The read values are not the same when I change the user clock, at 333.33 Mhz I have only a few values. When I read 20 datas the c3_p3_rd_empty is asserted after pushing the reading button 20 times. After reading 5 to 10 datas, I read the same value until the end.


I have set two unidirectionnal ports, p2 for writing and p3 for reading.


I have tried to send data with only one impulsion of c3_p2_wr_en (page 53 of the datasheet) and also with one impulsion for each change of the data (page 55 of the datasheet) but with no result.


I verified that the calibration is done and it's ok.


Do you know a tool to see the content of the DDR2 memory ? It can help us a lot because I can understand if the problem is due to the writing or the reading.


And do you have an idea for the clock configuration ? Maybe mine is wrong

 

Thank for your attention

 

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7 Replies
Xilinx Employee
Xilinx Employee
12,941 Views
Registered: ‎07-11-2011

Re: Atlys DDR2 memory

Hi,

 

Your cloking looks fine.

User clocks can also be asynchronous to memory clock so there should not be any issue.

Did you try to program example design and error status is zero/high?

Hope you are directly testing your design on HW, instead I would suggest you to run simulation so that you can view data at DDR3 interface level which can give you clues on what is going wrong.

If possible post your chipscope or simulation dumps to analyze the issue.

 

Regards,

Vanitha

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Visitor maxlutece
Visitor
12,933 Views
Registered: ‎07-30-2014

Re: Atlys DDR2 memory

Thanks for your answer.

 

I tried to launch the example design but there is a Verilog file among the VHD files and it produces an error when synthetizing on ISE so I didn't lost more time on it.

 

I did some simulations to show you how my program communicates with the DDR2, of course we don't see any response from DDR2 here as it is HW :

 

1- I load the write FIFO with 25 values while p2_wr_en is high :

LoadWriteFIFO.PNG

 

2- I push the "btn3" to do the command enable to write the data into the DDR2 at address 00...001 (p2_cmd_en high) with burst length = 25 :

WritingMemory.PNG

 

3- I push the "btn2" to launch the read from the DDR2 at address 00...0001 with burst length = 25, the data should fill the FIFO of the port 3 (used to read the DDR2) :

ReadData.PNG

 

4- I push the "btn5" to release the data at the output of the read FIFO and to output the next data (I do this operation several times) :

LoadReadFIFO.PNG

 

You can see all the important signals I use to drive tis DDR2 memory.

The calibration goes well as I put the "calib_done" signal on a LED which is on.

 

Thank you again for your help.

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Visitor maxlutece
Visitor
12,906 Views
Registered: ‎07-30-2014

Re: Atlys DDR2 memory

I understand that if I could find a simulation model of my memory part EDE1116AXXX-8E or MIRA P3R1GE3EGF-G8E it would be easier for the simulation. Because there would be responses from the simulation model and I could see what's wrong with my simulation

 

But I don't find yet ...

 

Regards

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Xilinx Employee
Xilinx Employee
12,901 Views
Registered: ‎07-11-2011

Re: Atlys DDR2 memory

Hi,

 

All your waveforms show User nterface, but to know if commands are accepted by MIG and to monitor the data at phy level  simulation is the best way.

Otherwise you need to probe your board to see what actually is happening.

 

I assume you have generated MIG using base part and by changing address/timing parameters that suit your actual part.

If yes, MIG would Micron simulation model and pass your timing paranters using which you should be able to do the simulation and writes and reads.

 

Regards,

Vanitha

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Visitor maxlutece
Visitor
12,898 Views
Registered: ‎07-30-2014

Re: Atlys DDR2 memory

 

I don't have set these values, I let the defaults parameters. In the datasheet (http://www.digilentinc.com/Data/Products/ATLYS/Atlys_rm_V2.pdf) of Atlys Board they say "

selecting the “EDE1116AXXX-8E” device will result in the correct timing parameters being set." 

 

 

DDR2_MIG_Timing_parameters.PNG 

 

Do you think somethng is wrong with that ?

 

I have already search on the Micron website but I set the AS parameter to 'disabled' which imply that we don't have the DQS_N and UDQS_N signals. These signals are in simulation model and I don't know how to do with these. Moreover the model is in verilog and I don't  know how to mix VHDL and Verilog files.

 

Thanks

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Xilinx Employee
Xilinx Employee
12,875 Views
Registered: ‎07-11-2011

Re: Atlys DDR2 memory

Hi,

 

Elpida Is Now Micron, so please find a MIcron part that is similar to Elpida part and generate MIG so that you can use Micron memory model.

 

In your first snapshot I see command clock is not toggling  initially but you have asserted p2_wr_en?

I do not see calib_done signal in your waves? 

Did you wait till PLL/MMCM is locked and calibration is done and then only started your command interface?

I suspet if your commands are not accepted by the controller as I do not see cmd_empty pulled low.

Would it be posssible to upload your zipped project for investigation ?

 

Regards,

Vanitha

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Visitor maxlutece
Visitor
12,870 Views
Registered: ‎07-30-2014

Re: Atlys DDR2 memory

Thanks for your help

 

In fact I don't have any simulation model in  my project so I cannot get response from the DDR2 outputs like  calib_done and cmd_empty. Then when I simulate I delete the calib_done condtion, it's for that the PLL are not ready when I assert p2_wr_en.

 

Reagrds

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