10-24-2016 05:20 AM
I am using spartan 6 FPGA. I am writing a set of values from vhdl side to BRAM memory and read it out at the microblaze side.
But when I read from microblaze side I doubt if all the values I am giving to the bram from VHDL side is not written. and again writing resumes after a time period. Is it possible? Does the bram have some refresh cycle or something that halts operation. Data is written at rate of 150kbps and read out at same rate. Also I use cache on microblaze side. Will this cause some sort of delay (or interruption in between) in the reading side?
Thanks in advance.
10-24-2016 06:49 AM
If you are using cache on the shared BRAM, you need to invalidate the cache before reading in order to get the most recently written data. There is nothing within the BRAM itself that would delay the write operations. Only the cache system would do that.
11-17-2016 01:57 AM
Sorry for delay in reply . I have been in some other project for sometime. I noticed one more issue. In microblaze I have enabled cache for DDR memory access and the segments like .bss lies in the DDR memory. I started a timer and read a single value from BRAM,got value from timer for eg cnt and stopped timer . I am getting different values for cnt each time I run program. Why does this happen? The value has to be same since we should take same time period to read a single value from BRAM each time.