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Explorer
Explorer
11,492 Views
Registered: ‎07-04-2014

Clock has multiple drivers

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Hi All, I have the following code

 

1) Input clock pin is 125MHz here is a buffer

IBUFG I_IBUFG(
      .O		(I_CLK125M_IBUFG),
      .I		(CLK125M)
   );

 Then the I_CLK125M_IBUFG  goes into multiple input pin of different modules:

 

a) It goes first into a PLL with "no buffer", "interal" compensation and "clkfbout" feedback options chosen.

 

clk_gen I_CLK_GEN
   (// Clock in ports
    .CLK_IN1		(I_CLK125M_IBUFG),      
    // Clock out ports
    .CLK_OUT1		(CLOCK_50MHZ),    
    .CLK_OUT2		(I_SAMPLING_CLK),    
    .CLK_OUT3		(I_DIV_CLOCK),    
    
    // Status and control signals
    .RESET			(1'b0),// IN
    .LOCKED			(I_PLL_LOCKED)); 

 b) it also goes to the Ethernet module input

 

MAC_top U_MAC_top(
.Clk_125M	(I_CLK125M_IBUFG  ),
others connections.... );

 c) and finally goes into a DDR3 (MIG generated module)

u_ddr3_if (
		
      .c1_sys_clk			(I_CLK125M_IBUFG),
      .c1_sys_rst_i			(I_RESET_DDR),
other connections);

 

It will synthesize correctly.. However, implementation complains about:

 

ERROR:NgdBuild:455 - logical net 'I_CLK125M_IBUFG' has multiple driver(s):
ERROR:NgdBuild:462 - input pad net 'I_CLK125M_IBUFG' drives multiple buffers:
ERROR:NgdBuild:947 - input pad net 'I_CLK125M_IBUFG' is driving non-input
buffer(s):

 

What am I doing wrong?

 

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Explorer
Explorer
12,057 Views
Registered: ‎07-04-2014

Re: Clock has multiple drivers

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I found the solution. I had the same clock that was re-routed to an output pin somewhere. I had to add a ODDR2 buffer and it worked.

View solution in original post

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Explorer
Explorer
11,490 Views
Registered: ‎07-04-2014

Re: Clock has multiple drivers

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Ok.. I found the error. The MIG generated another IBUGF in the infrastructure.v file.

 

I removed that and it works now.

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Explorer
Explorer
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Registered: ‎07-04-2014

Re: Clock has multiple drivers

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Ok.. it worked.. but now I have another problem that is related to the previous error I think.

 

 

The software complains that:

 

Place:1172 - The BUFLL/BUFPLL_MCB instance <u_ddr3_if/memc1_infrastructure_inst/BUFPLL_MCB1> needs to have all of its IOB loads placed into its same IO bank. However, due to user-specified constraints, the BUFLL/BUFPLL_MCB instance <u_ddr3_if/memc1_infrastructure_inst/BUFPLL_MCB1> and its IOB load <DDR3_UDQS> cannot be placed in the same IO bank.

 

These constraints could be LOCATION or AREA constraints on  <u_ddr3_if/memc1_infrastructure_inst/BUFPLL_MCB1>, or <DDR3_UDQS>, or other components connected to them, which could impose an implicit constraint on them. Please check user-specified constraints on all of these components to ensure their combination is not infeasible.

 

What is the problem??? 

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Xilinx Employee
Xilinx Employee
11,474 Views
Registered: ‎07-01-2010

Re: Clock has multiple drivers

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Hi,

 

Can you check if too many GCLK pins in the two IOB banks have been occupied (used as general purpose I/O)? This may result, the tool fails to find optimal GCLK pins for these two input clocks that feed PLL.In such cases freeing the GCLK will fix the issue.

 

Regards,

Achutha

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Explorer
Explorer
11,473 Views
Registered: ‎07-04-2014

Re: Clock has multiple drivers

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Hi, thanks for you help.

 

I will be using a dev. board, so the input clock pin (CLK125M) is at AA12 which is in bank2. The DDR is in bank1 (although I could configure it to use bank3 DDR). 

 

To answer your question directly:

 

In bank1 (which is plugged to the DDR) all GCLK pins are used.

In bank 2 (where the CLK125M is input) 3 out of 8 GLCK pins are assigned to something. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-01-2010

Re: Clock has multiple drivers

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Hi,

Can you try to free one GCLK in bank1 and lock AA12 to it and see if that helps?

Regards,
Achutha
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Explorer
Explorer
11,434 Views
Registered: ‎07-04-2014

Re: Clock has multiple drivers

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Hi,

 

I did tried what you suggested, but got the same error. I will keep on working with that.. if you got any other ideas, don't hesitate.

 

Thanks

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Explorer
Explorer
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Registered: ‎07-04-2014

Re: Clock has multiple drivers

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Here is something that may help other people help me!

 

1) Input clock is AA12 in bank2

2) IBUFG takes the input clock from bank2 and place a buffer in clock region X0Y0

 

Then that buffered clock is going to 2 places:

a) The clock generator (which has a BUFG as input)

b) The DDR3 (MIG) module in bank 1  which has PLL_ADV instance

 

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Explorer
Explorer
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Registered: ‎07-04-2014

Re: Clock has multiple drivers

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If I add a BUFG to the DDR3 module, here is the error

 

A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component <CLK125M> is placed at site <AA12>. The corresponding BUFG component <I_CAM_CLK_GEN/I_IBUFG2> is placed at site <BUFGMUX_X3Y6>.

There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.

A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "CLK125M" CLOCK_DEDICATED_ROUTE = FALSE; >

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Explorer
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Registered: ‎07-04-2014

Re: Clock has multiple drivers

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I tried repositionning the DDR3 module in bank3 and got the same error. ""ConstraintResolved NO placeable site for..." and "SIO has over-constrained componet..."

 

I tried using another 100Mhz clock generated by the input PLL. The error on the DDR3 module is now replaced by the same error on another module. I get "ConstraintResolved NO placeable site for u_cam_in/bufpll_inst" which is a SelectIO interface for a camera. (LVDS receiver).

 

I also have this warning " All members of TNM group "u_ddr3_if_memc3_infrastructure_inst_clk0_bufg_in" have been optimized out of the design." Could this be the source of the problem?

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Explorer
Explorer
12,058 Views
Registered: ‎07-04-2014

Re: Clock has multiple drivers

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I found the solution. I had the same clock that was re-routed to an output pin somewhere. I had to add a ODDR2 buffer and it worked.

View solution in original post

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