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Visitor kxdeng
Visitor
24,520 Views
Registered: ‎11-03-2009

Clock issue about spartan 6.

It's impossible to implement the top design because I want to generate a clock to drive both FPGA logic and OPAD using DCM. the ERROR message following.

ERROR:Place:1206 - This design contains a global buffer instance,
   <cw_0/clkout1_buf>, driving the net, <clk_98m_OBUF>, that is driving the
   following (first 30) non-clock source pins off chip.
   < PIN: clk_98m.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue. Although the net
   may still not route, you will be able to analyze the failure in FPGA_Editor.
ERROR:Place:1136 - This design contains a global buffer instance,
   <cw_0/clkout1_buf>, driving the net, <clk_98m_OBUF>, that is driving the
   following (first 30) non-clock source pins.
   < PIN: clk_98m.O; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue.
   < PIN "cw_0/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

Who can tell what should I do? Thanks a lot.

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36 Replies
Historian
Historian
24,492 Views
Registered: ‎02-25-2008

Re: Clock issue about spartan 6.

Carefully read the error message. It gives a very good solution. Read the part that starts, "It is recommended to ..."
----------------------------Yes, I do this for a living.
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Observer asangare
Observer
24,460 Views
Registered: ‎12-08-2009

Re: Clock issue about spartan 6.

Assuming you are using Verilog, you should do this:

ODDR2 #(
   // The following parameters specify the behavior
   // of the component.
   .DDR_ALIGNMENT("NONE"), // Sets output alignment
                           // to "NONE", "C0" or "C1"
   .INIT(1'b0),    // Sets initial state of the Q 
                   //   output to 1'b0 or 1'b1
   .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC"
                   //   set/reset
)
ODDR2_inst (
   .Q(clk_98m),   // 1-bit DDR output data
   .C0(clkout1), // 1-bit clock input
   .C1(clkout1_n), // 1-bit clock input
   .CE(CE), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
);

where clkout1 is the clock that you are dring out and clkout1_n is the inverse of the clkout1 (you would need to generate this clock with the DCM - it is basically clkout1 with a 180° phase shift)
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Xilinx Employee
Xilinx Employee
24,454 Views
Registered: ‎11-28-2007

Re: Clock issue about spartan 6.

Please note that there are several options on clock sources for ODDR and IDDR C0 and C1 inputs depending on your application (see the snapshot below). Using DCM CLK0 and CLK180 is just one of the options.

 

 

Cheers,
Jim
ScreenHunter_031.gif
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Newbie jankzov.x
Newbie
23,874 Views
Registered: ‎07-22-2010

Re: Clock issue about spartan 6.

I'm totally new to Xilinx FPGAs (not to the FPGA world, though), and I ran into the same problem.

 

I tried the solution suggested by both Jimwu and ISE, and it works.

But I cannot believe you need to use such a "trick" to output a clock from a PLL.

 

Does this occur because the output pin I use is not a "clock source pin"?

Are GCLK pins unappropriate pins to output a clock?

Do I have to tell the tool somehow that the signal I'm trying to output is indeed a clock signal, not just an ordinary signal?

 

I'm a little confused here.

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Historian
Historian
23,864 Views
Registered: ‎02-25-2008

Re: Clock issue about spartan 6.

 


@jankzov.x wrote:

I'm totally new to Xilinx FPGAs (not to the FPGA world, though), and I ran into the same problem.

 

I tried the solution suggested by both Jimwu and ISE, and it works.

But I cannot believe you need to use such a "trick" to output a clock from a PLL.

 


 

 

The source of the clock being output does not have to come from a DLL or PLL. It can also come from any global clock net.

 

 

 


 

Does this occur because the output pin I use is not a "clock source pin"?

Are GCLK pins unappropriate pins to output a clock?

 


 

 

No, clock source pins (GCLK, local/region clock, etc) are for clock INPUTs. As noted elsewhere, clock OUTPUTs may be on any pin that supports the IOSTANDARD required by the system. (So you could use a GCLK pin as an output, but when doing so, it's not a GCLK pin, it's just a regular I/O pin. GCLK pins are special because they connect directly to global clock buffers if the signal is actually a clock.)

 

 


Do I have to tell the tool somehow that the signal I'm trying to output is indeed a clock signal, not just an ordinary signal?

 


 

No, it's just an ordinary signal.

 

Anyways -- the reason for using the ODDR for clock output is simple. The global clock networks do not (easily) connect to both clock inputs (flip-flop, BRAM, whatever) and regular logic resources (LUT inputs, OBUFs, whatever). They complain about this, and it degrades timing and has all sorts of other issues. So using the ODDR clock simplifies matters greatly: you get a clock output synchronous with the FPGA's internal clock, the clock routing inside the FPGA sees only clock loads and the tools are happy.

----------------------------Yes, I do this for a living.
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Observer julio_avr
Observer
22,459 Views
Registered: ‎12-09-2010

Re: Clock issue about spartan 6.

The suggested ODDR2 solution only works for single ended output clock, but doesn't when the output is differential (ODDR2 can't drive an OBUFDS), and the Spartan3 solution (a FDDCE driving an OBUFDS) would require generating a 2x clock. Any suggestions (other than dedicating a DCM)?


I used a DCM output to directly (no BUFG) drive the OBUFDS maps and places fine, but I don't know how this performs compared to using an ODDR2 as suggested, and limits the number of clocks you can forward in a small device.


Thanks!

 

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Xilinx Employee
Xilinx Employee
22,453 Views
Registered: ‎01-03-2008

Re: Clock issue about spartan 6.

> The suggested ODDR2 solution only works for single ended output clock, but doesn't when

> the output is differential (ODDR2 can't drive an OBUFDS)


That isn't right.  The ODDR2 can drive the OBUFDS it is used this way all of the time.  Where did you read that this wasn't possible?

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
Observer julio_avr
Observer
22,449 Views
Registered: ‎12-09-2010

Re: Clock issue about spartan 6.

I was getting an mapping error message with ISE 12.3 yesterday, but now seems fine, driving the ODDR2 either directly from a PLL or through a BUFG, so I withdraw my comment.... odd.. could be related to other issues I had mapping a couple of clocks.

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Xilinx Employee
Xilinx Employee
21,604 Views
Registered: ‎11-28-2007

Re: Clock issue about spartan 6.

If the IOSTANDARD you used happens to be LVDS, Spartan6 does have a restriction on where the differential outputs can be placed: bank 1 and 3 can *NOT* be used for LVDS outputs on a Sparatan6 device. That might be the error you were seeing.

 

 


@julio_avr wrote:

I was getting an mapping error message with ISE 12.3 yesterday, but now seems fine, driving the ODDR2 either directly from a PLL or through a BUFG, so I withdraw my comment.... odd.. could be related to other issues I had mapping a couple of clocks.


 

Cheers,
Jim
Observer julio_avr
Observer
14,473 Views
Registered: ‎12-09-2010

Re: Clock issue about spartan 6.

Hi Jim,

 

For the purposes of clock forwarding using an ODDR2, it seems the limitation of locally inverting the GCLK that I want to forward is some duty cycle distortion (UG382, May 12/2011 page 34), is this correct?

 

The same document suggests using local inversion for clock forwarding (figures 3-13,3-14, zero delay buffer using a PLL), but there are no guidelines as to when this is OK.

 

Under which conditions (i.e. frequency, output jitter, allowable duty cycle distorsion tolerance ...) would you say it's OK to just locally invert one of the clocks for the ODDR2?

 

I need to forward 5 clocks (61 to 250MHz range) in a Spartan6 based design, and I might not be able to afford the extra 5 BUFGs and related PLL/DCM outputs, so being able to judge when to use the simpler solution would be handy.

 

Thanks!

 

Julio

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Instructor
Instructor
14,468 Views
Registered: ‎07-21-2009

Using ODDR2 to forward a clock to output in spartan 6

For the purposes of clock forwarding using an ODDR2, it seems the limitation of locally inverting the GCLK that I want to forward is some duty cycle distortion (UG382, May 12/2011 page 34), is this correct?

 

There is nothing on page 34 which bears on this question.  Instead, see UG382 Figure 3-14 for an example of using ODDR2 to forward a clock to external pins as a diff pair (using OBUFDS as output buffer, no less!).  Notice that the global clock is inverted at the ODDR2 clock input.  The ODDR2 block has the inverter 'built in'.

 

In UG381, look up Table 2-5.  Note that both C0 and C1 clock inputs to the ODDR2 block are (individually) optionally invertible.

 

Does this answer your question?

 

-- Bob Elkind

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Observer julio_avr
Observer
14,452 Views
Registered: ‎12-09-2010

Re: Using ODDR2 to forward a clock to output in spartan 6

Hi Bob ...

 

Risking being a bit peeky, I'm mostly interested in the criteria (i.e. clock frequency, timing margins, duty cycle distorsion tolerance, clock forwarding vs data handling with IDDR2/ODDR2) to determine which option is acceptable to provide the inverted clock:

-local inversion (UG381, fig 2-2) - simpler, less resources

-inverted global clock (uses extra DCM/PLL output and a BUFG)

 

From UG381(May12) page 31 (clocking for IDDR2/ODDR2):

"The following options can be used for clocking IDDR2 and ODDR2 primitives.

• When performance is not critical, use a single DCM output to drive both clock (C0)and the inverted clock (C1) using local inversion. Works with or without IODELAY2.

• For the highest performance, use two DCM outputs with separate BUFGs with 180°phase difference. Works with or without IODELAY2. See Figure 1-18."

 

From page 34, and fig 1-18 (mind you, it's in the "examples of high speed I/O network clocking"):

"To maintain the best duty-cycle performance using the DCM, use separate DCM clock outputs to drive C0 and C1. Each DCM output drives a separate global buffer. While possible using the BUFG to invert one phase locally within the I/O tile, it is not recommended as locally inverting one of the clocks inserts duty-cycle distortion."

 

Thank you! :D

 

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Instructor
Instructor
14,449 Views
Registered: ‎07-21-2009

Re: Using ODDR2 to forward a clock to output in spartan 6

There is nothing more that I could add to what you've already read.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Observer gordwait
Observer
14,186 Views
Registered: ‎09-18-2007

Re: Using ODDR2 to forward a clock to output in spartan 6

I'm looking to push out a copy of an internal 125 Mhz global clock without using up a second GCLK tree, and without a PLL or DCM.. An ODDR2 output with a lax duty cycle would do me fine..

 

So far I can't get it configured.

 

It seems UG381 has been updated.

 

The sections you quote are no longer in the UG381,  (December edition) making me think this isn't actually a feature of the Spartan 6 family..

 

I see the comments on the ODDR2 C0 and C1 (invertible) but there doesn't seem to be any way to set the inversion in a VHDL instantiation. As well the ODDR2 section does not mention it or show it in the block diagram.

 

Confused...

 

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Instructor
Instructor
14,181 Views
Registered: ‎07-21-2009

Re: Using ODDR2 to forward a clock to output in spartan 6

I'm looking to push out a copy of an internal 125 Mhz global clock without using up a second GCLK tree, and without a PLL or DCM.. An ODDR2 output with a lax duty cycle would do me fine.

 

You don't need a second BUFG tree.  One will do just fine.  See this thread on a very similar subject, where a single BUFG-driven clock drives both .C0 and .C1 clock inputs to ODDR2 primitive.  While the code snippets are in Verilog, VHDL conversion should be trivial.

 

I see the comments on the ODDR2 C0 and C1 (invertible) but there doesn't seem to be any way to set the inversion in a VHDL instantiation.

 

noninverted clock:  "my_clock"

inverted clock:  "!my_clock" or "~my_clock" or "NOT my_clock" (this is my guess, I'm not a VHDL user)

 

As well the ODDR2 section does not mention it or show it in the block diagram.

 

See UG381, Table 2-5, descriptions for C0 and C1 clock inputs: "optionally invertible".

Also see UG382, Figure 3-14.  Marked up and excerpted:

 

Are you convinced?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

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2. Search the forums (and search the web) for similar topics.
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Teacher rcingham
Teacher
14,160 Views
Registered: ‎09-09-2010

Re: Using ODDR2 to forward a clock to output in spartan 6

invert_my_clock:
my_inverted_clock <= not my_clock;

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Instructor
Instructor
14,151 Views
Registered: ‎07-21-2009

Re: Using ODDR2 to forward a clock to output in spartan 6

Thanks, RC! :smileyhappy:

 

How does this look? -- from the ISE HDL templates (click on the light bulb!):

 

   ODDR2_inst : ODDR2
   generic map(
      DDR_ALIGNMENT => "NONE",
      INIT => '0',
      SRTYPE => "SYNC")
   port map (
      Q => clock_output,    -- 1-bit output data
      C0 => my_clock,       -- 1-bit clock input
      C1 => (NOT my_clock), -- 1-bit clock input
      CE => 1,              -- 1-bit clock enable input
      D0 => 1,
      D1 => 0,
      R => 0,    -- 1-bit reset input
      S => 0     -- 1-bit set input
   );

 

I suspect this is simpler in Verilog than VHDL, especially since I more or less *understand* and use Verilog (and not VHDL).  Here's the Verilog example:

 

  ODDR2 #(
      .DDR_ALIGNMENT("NONE"),
      .INIT(1'b0),
      .SRTYPE("SYNC")
   ) ODDR2_inst (
      .Q   (clock_output), // 1-bit DDR output data
      .C0  (my_clock),     // 1-bit clock input
      .C1  (~my_clock),    // 1-bit clock input
      .CE  (1'b1),         // 1-bit clock enable input
      .D0  (1'b1),
      .D1  (1'b0),
      .R   (1'b0),   // 1-bit reset input
      .S   (1'b0)    // 1-bit set input
   );

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

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2. Search the forums (and search the web) for similar topics.
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Teacher rcingham
Teacher
14,147 Views
Registered: ‎09-09-2010

Re: Using ODDR2 to forward a clock to output in spartan 6

Unfortunately, use of constructs such as "not my_clock" in port maps is not supported. In-line function calls are for input ports, so you could define a function 'invert' that hides the 'not' functionalitly, and use that, but explictly inverting and using 'my_inverted_clock' is probably easier to understand in 2 years' time.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Instructor
Instructor
14,145 Views
Registered: ‎07-21-2009

Re: Using ODDR2 to forward a clock to output in spartan 6

Unfortunately, use of constructs such as "not my_clock" in port maps is not supported. In-line function calls are for input ports, so you could define a function 'invert' that hides the 'not' functionalitly, and use that, but explictly inverting and using 'my_inverted_clock' is probably easier to understand in 2 years' time.

 

Well, it works in Verilog :) even if it doesn't work in VHDL :(  I took (equivalent) Verilog code for a spin in ISE, to confirm it (see this thread).

 

If I was proficient in VHDL, I would post an example proof of the VHDL code...  but, alas, I am not proficient in VHDL.

Any volounteers?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Historian
Historian
17,883 Views
Registered: ‎02-25-2008

Re: Using ODDR2 to forward a clock to output in spartan 6


@eteam00 wrote:

Unfortunately, use of constructs such as "not my_clock" in port maps is not supported. In-line function calls are for input ports, so you could define a function 'invert' that hides the 'not' functionalitly, and use that, but explictly inverting and using 'my_inverted_clock' is probably easier to understand in 2 years' time.

 

Well, it works in Verilog :) even if it doesn't work in VHDL :(  I took (equivalent) Verilog code for a spin in ISE, to confirm it (see this thread).


 

This sort of construct (essentially functions in port maps) is not legal in versions of VHDL older than 2008. Of course, XST doesn't support it yet, almost four years after ratification.

 

 

----------------------------Yes, I do this for a living.
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Visitor lucky2
Visitor
17,858 Views
Registered: ‎06-17-2009

Re: Using ODDR2 to forward a clock to output in spartan 6

(This may be more of a synthesis question (XST) about controlling the ODDR2)

 

When I use a PLL (DCM) and single BUFG ODDR2 to drive a clock off chip I get a warning about creating a loop. (Xst:2016) C0 and C1 are driven by the same BUFG with an inversion on one input (C0 = CLK, C0 = ~CLK in Verilog). 

 

The inversion does not seem to be absorbed into the ODDR2 when I look at the technology schematics although the ODDR2 does show the inversion in the FPGA editor.  Is there something more that needs to be added to the primitive instantiation to avoid the warning?   The results are as expected, but there is a "loop" warning (XST 2016).

 

The better solution (no duty cycle error) with separate 180 deg clocks using 2 BUFGs and 2 outputs from the DCM does not have this warning and both C1 and C0 are as expected.

 

I am using a Spartan 6 with ISE 13.2.

 

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Instructor
Instructor
17,854 Views
Registered: ‎07-21-2009

Re: Using ODDR2 to forward a clock to output in spartan 6

The inversion does not seem to be absorbed into the ODDR2 when I look at the technology schematics although the ODDR2 does show the inversion in the FPGA editor.

 

In post #16 in tthis thread, there is a  link to another thread which resolves your problem straight on.

 

(SPOILER ALERT)  The answer is that the so-called 'internal' inverters in the ODDR2 block are not 'internal' as far as the technology or RTL schematics are concerned.  These 'internal' inverters are, in fact, logically and physically located in the interconnect 'switchbox'.  Which brings up another, related implementation consideration:  BUFGs can connect to these inverters-in-a-switchbox, but BUFIOs cannot (in the context of Spartan-6).  If you are using BUFIOs, you must use two of them -- one non-inverting and the other inverting -- to drive the ODDR2 in a clock-forwarding configuration.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Highlighted
Adventurer
Adventurer
17,589 Views
Registered: ‎06-26-2008

Re: Using ODDR2 to forward a clock to output in spartan 6

	-------------------------------------------
	---	Clock Output						---
	-------------------------------------------
	--use ODDR2 to connect the clocks
	do_clk_b <= not(do.clk);
	aoclk_oddr : ODDR2
	port map(
		C0 => do.clk,
		C1 => do_clk_b,
		CE => '1',
		D0 => '1',
		D1 => '0',
		Q => ao_clk_i,
		R => '0',
		S => '0'
		);
	aoclk_obuf : OBUF
	port map(
		I => ao_clk_i,
		O => ao.clk
	);
	ao.vid <= do.vid;

 I use the above code for the clocking out.  But I get a warning about clock loops:

 

WARNING:Xst:2016 - Found a loop when searching source clock on port 'do_clk_b:do_clk_b'

 

Am I doing this correctly?

 

 

Tags (1)
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Instructor
Instructor
17,585 Views
Registered: ‎07-21-2009

Re: Using ODDR2 to forward a clock to output in spartan 6

Suggestions:

 

  • change the name of signal do_clk_b in your code snippet.
  • post the code which describes how clock do_clk is generated
  • post the code which describes ao.clk connections
  • open your design in FPGA editor to verify do_clk, do_clk_b are connected as intended.
  • Are there other warning messages?  If so, please post them.

-- Bob Elkind

SIGNATURE:
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Adventurer
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Registered: ‎06-26-2008

Re: Using ODDR2 to forward a clock to output in spartan 6

Hi Bob, attached is the wiring from the FPGA editor.

 

seems like the clocks are wired locally.  The ODDR2 seems to be wired correctly.

 

As for your questions

1.  changing the name of do_clk_b - do you mean to say that XST is incorrectly identifying my symbol as something that is generated automatically?  I have tried changing the name of  this net and the error is still there

2.  Do does not go into any DCM, it is merely an external clock that goes into a BUFGMUX with another clock signal.

3.  AO.clk is connected directly to an pin

4.  Attached diagram is the connections from the fpga editor.

5.  All other messages does not mention this net or clocks related to this net.  When I remove the ODDR2 and connect do.clk directly to the ao.clk pin, the error dissappears (of course the ODDR and the OBUF dissappears as well).

 

Thanks,

-J

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Instructor
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Registered: ‎07-21-2009

Re: Using ODDR2 to forward a clock to output in spartan 6

 

  • change the name of signal do_clk_b in your code snippet.
  • post the code which describes how clock do_clk is generated
  • post the code which describes ao.clk connections
  • open your design in FPGA editor to verify do_clk, do_clk_b are connected as intended.
  • Are there other warning messages?  If so, please post them.

As for your questions

1.  changing the name of do_clk_b - do you mean to say that XST is incorrectly identifying my symbol as something that is generated automatically?

 

possible, or the same signame appears more than once in your code

 

I have tried changing the name of  this net and the error is still there

 

Did the error message flag the old signame or the new signame?

 

2.  Do does not go into any DCM, it is merely an external clock that goes into a BUFGMUX with another clock signal.

 

Suggest you post *all* your code which defines the two clock inputs to the BUFGMUX and the SEL input to the BUFGMUX.  Is the SEL input a register output?

 

We're trying to help you debug this problem.  Some designers post too much code, some designers are reluctant to post enough code.  You seem to be reluctant to post enough code, and we need more information than what you are providing.

 

3.  AO.clk is connected directly to an pin

 

Anything else, or only the pin?  You have given us a partial answer, not a full answer.

 

For what it's worth, the following code seems to represent as much of your circuit which you have seen fit to disclose, and it compiles without errors or warnings to a Spartan-6 device.  Even though it is written in Verilog instead of VHDL,  this should be useful information for you.

 


module s6_forum_top (inclock_a, inclock_b, clock_sel, outclock);
    input        inclock_a, inclock_b, clock_sel;
    output    outclock;

    wire intclock;

   BUFGMUX #(.CLK_SEL_TYPE("ASYNC"))
   BUFGMUX_inst (
      .O     (intclock),     // 1-bit output: Clock buffer output
      .I0    (inclock_a),    // 1-bit input: Clock buffer input (S=0)
      .I1    (inclock_b),    // 1-bit input: Clock buffer input (S=1)
      .S     (clock_sel) );  // 1-bit input: Clock buffer select

   ODDR2 #(
      .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
      .SRTYPE    ("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
   ) ODDR2_inst (
      .Q     (outclock),   // 1-bit DDR output data
      .C0    (intclock),   // 1-bit clock input
      .C1    (~intclock),  // 1-bit clock input
      .CE    (1'b1),       // 1-bit clock enable input
      .D0    (1'b1),       // 1-bit data input (associated with C0)
      .D1    (1'b0),       // 1-bit data input (associated with C1)
      .R     (1'b0),       // 1-bit reset input
      .S     (1'b0) );     // 1-bit set input

endmodule

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Registered: ‎06-26-2008

Re: Using ODDR2 to forward a clock to output in spartan 6

Thanks Bob for the quick response.  My apologies for not posting enough code.  I was under the impression that this might be a well understood problem and it would be very obvious to troubleshoot (ie. a syntax/coding error).  Here's the code for the BUFGMUX.  

 

	--switch the synthetic clock with the left and right clocks first
	synth_clkl : BUFGMUX
	port map(
		O => clksyn,
		I0 => clkfx,
		I1 => din.clk,
		S => vdet_i);

	--register the video input signals, to sync timing
	dout.clk <= clksyn;
	dout.vid <= din.vid;

clkfx is a synthesized clock signal from a DCM.  This is rarely selected.

vdet_i is NOT as registered output.  I'd like to understand how this affects the outcome.  Usually this is set to high, which means that din.clk is selected (and rarely changes).  din.clk comes directly from an input pin.  This clock is used to clock other flipflops before and after the bufgmux.  Dout.clk eventually becomes do.clk in the higher-up module.

 

here are some more information.

 

- The error flags the name of the NEW signal

- AO.clk is ONLY connected to a pin, it is renamed because XST doesn't support composite records when connecting to external pins:

 

	 tx_an_clk <= ao.clk;  --which is then defined in the UCF file

 

A quick question, what is meant by a loop in the source clock?  What should we see on the FPGA editor with the connections if such a loop exists?

 

In o

 

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Instructor
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Registered: ‎07-21-2009

Re: Using ODDR2 to forward a clock to output in spartan 6

A quick question, what is meant by a loop in the source clock?  What should we see on the FPGA editor with the connections if such a loop exists?

 

Is it possible that the BUFGMUX output clock is involved in the logic which generates the BUFGMUX select input, or one of the BUFGMUX input clocks, or the DCM which drives one of the BUFGMUX inputs?  Any of these possibilities might be a 'loop'

 

If you replace BUFGMUX with a simple BUFG (or tie the select input to a fixed logic '0' or '1'), does the warning message still appear?

 

Keep in mind, a warning message is not the same as an error message.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Registered: ‎02-27-2012

Re: Using ODDR2 to forward a clock to output in spartan 6

I'm using ODDR2 to generate an external clock (ISE = 13.1, Planahead = 13.1):

 

clk5m_inst : ODDR2
   generic map
 (
      DDR_ALIGNMENT => "NONE",  -- Sets output alignment to "NONE","C0", "C1"
      INIT => '0',      -- Sets initial state of the Q output to '0' or '1'
      SRTYPE => "SYNC"    -- Specifies "SYNC" or "ASYNC" set/reset
 )
   port map
 (
      Q => clk_alc,      -- 1-bit output data
      C0 => clk5m,     -- 1-bit clock input
      C1 => not(clk5m),    -- 1-bit clock input
      CE => n_enable_clock,    -- 1-bit clock enable input
      D0 => '0',        -- 1-bit data input (associated with C0)
      D1 => '1',        -- 1-bit data input (associated with C1)
      R => reset,      -- 1-bit reset input
      S => '0'          -- 1-bit set input
   );

 

But when i try to connect the Q output with Planahead program I have the message:

"Conflicting nets for physical connection driven by OLOGIC_X12Y33.OSRUSED.OUT: U_0............. GROUND"

 

In the primitive ODDR2, SET and RESET are 2 input pins, but Planahead sees them as 1 pin.

What can I do?

Can I place on ucf file this FPGA pin without Planahead and without problems?

Thanks

mp
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