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Visitor
Visitor
24,852 Views
Registered: ‎11-03-2009

Clock issue about spartan 6.

It's impossible to implement the top design because I want to generate a clock to drive both FPGA logic and OPAD using DCM. the ERROR message following.

ERROR:Place:1206 - This design contains a global buffer instance,
   <cw_0/clkout1_buf>, driving the net, <clk_98m_OBUF>, that is driving the
   following (first 30) non-clock source pins off chip.
   < PIN: clk_98m.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue. Although the net
   may still not route, you will be able to analyze the failure in FPGA_Editor.
ERROR:Place:1136 - This design contains a global buffer instance,
   <cw_0/clkout1_buf>, driving the net, <clk_98m_OBUF>, that is driving the
   following (first 30) non-clock source pins.
   < PIN: clk_98m.O; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue.
   < PIN "cw_0/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

Who can tell what should I do? Thanks a lot.

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Instructor
Instructor
10,509 Views
Registered: ‎07-21-2009

Marco,

 

There are a number of things which can be causing the problem you describe.

Please open a new thread in the Spartan forum to continue discussion of this problem.

 

-- Bob Elkind

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Visitor
Visitor
10,103 Views
Registered: ‎12-17-2012

Hi every one. This is my first post in xilinx user community. I am using EDK 13.4 and SP605. I want to connect external ADC with SP605. But I have same clock problems and I don't know how to  fix this in edk. I connected the clock generator output to external pin but it shows error with suggestion of using clock forwarding technique. I don't know how to use this here. Plz help me.

Tags (1)
clk_generator.jpg
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Highlighted
Visitor
Visitor
9,858 Views
Registered: ‎05-29-2013

Hello!

 

I need to forward clock to an external ADC. My clock input is 48 MHz. I use a DCM to create a divided clock (I need 24 MHz). Then I forward the new clock (24 MHz) via an ODDR2 to the external device. I'm using the Spartan 6 FPGA.

 

The problem is: the forwarded clock has a very high skew. It's getting better if I lower the frequency. AND there is absolutely no difference whether I use a ODDR2 or dont - the oscilloscope shows the same waveform.

 

The CLK output pin is a LVTTL IO standard. The inverted clock is generated using a logic statement (I tried also to instantiate another DCM but it had no effect at all).

 

I attached the Osciloscope output.

 

DCM instantiation:

 

DCM_SP_inst : DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- CLKDV divide value
-- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
CLKFX_DIVIDE => 2, -- Divide value on CLKFX outputs - D - (1-32)
CLKFX_MULTIPLY => 2, -- Multiply value on CLKFX outputs - M - (2-32)
CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
CLKIN_PERIOD => 20.8333, -- Input clock period specified in nS
CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X)
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DSS_MODE => "NONE", -- Unsupported - Do not change value
DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
FACTORY_JF => X"c080", -- Unsupported - Do not change value
PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
port map (
CLK0 => s_clk0, -- 1-bit output: 0 degree clock output
CLK180 => open, -- 1-bit output: 180 degree clock output
CLK270 => open, -- 1-bit output: 270 degree clock output
CLK2X => open, -- 1-bit output: 2X clock frequency clock output
CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
CLK90 => open, -- 1-bit output: 90 degree clock output
CLKDV => s_clk_half, -- 1-bit output: Divided clock output
CLKFX => s_clk_full, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
LOCKED => open, -- 1-bit output: DCM_SP Lock Output
PSDONE => open, -- 1-bit output: Phase shift done output
STATUS => open, -- 8-bit output: DCM_SP status output
CLKFB => s_clk0, -- 1-bit input: Clock feedback input
CLKIN => in_clk, -- 1-bit input: Clock input
DSSEN => '0', -- 1-bit input: Unsupported, specify to GND.
PSCLK => '0', -- 1-bit input: Phase shift clock input
PSEN => '0', -- 1-bit input: Phase shift enable
PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input
RST => '0' -- 1-bit input: Active high reset input
);

 

ODDR2 instantiation (it's in another component/file):

 

ODDR2_inst : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => out_adc_sclk, -- 1-bit output data
C0 => in_clk, -- 1-bit clock input
C1 => in_inv_clk, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => in_rst, -- 1-bit reset input
S => '0' -- 1-bit set input
);

 

 

Does somebody know what the problem is? Thank You!

MAP005.gif
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Highlighted
Historian
Historian
9,848 Views
Registered: ‎02-25-2008


@alexejluft wrote:

Hello!

 

I need to forward clock to an external ADC. My clock input is 48 MHz. I use a DCM to create a divided clock (I need 24 MHz). Then I forward the new clock (24 MHz) via an ODDR2 to the external device. I'm using the Spartan 6 FPGA.

 

The problem is: the forwarded clock has a very high skew. It's getting better if I lower the frequency. AND there is absolutely no difference whether I use a ODDR2 or dont - the oscilloscope shows the same waveform.

 

The CLK output pin is a LVTTL IO standard. The inverted clock is generated using a logic statement (I tried also to instantiate another DCM but it had no effect at all).

 

I attached the Osciloscope output.

 

Does somebody know what the problem is? Thank You!


well, let's ignore the zombie thread hijack for a moment, and just say: your 'scope photo shows only one trace, and skew is the time difference between one signal and another. So to say that the "forwarded clock has very high skew" is meaningless because you're not measuring it with respect to anything.

----------------------------Yes, I do this for a living.
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Highlighted
Visitor
Visitor
9,840 Views
Registered: ‎05-29-2013

I'm sorry, it was a wrong expression then, my english is not that great.

 

What I meant was that the output clock signal is not a square wave anymore, which it should be, I suppose. Or am I wrong and this is normal and usually doesn't cause any problems in practice?

 

Thank you.

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Highlighted
Visitor
Visitor
9,837 Views
Registered: ‎05-29-2013

And --- the amplitude is not really LVTTL like. I will test it on real hardware later.

 

The bandwith of the scope is only 50 MHz. So it could be that the scope shows a sine wave even though it's a square.

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Highlighted
Historian
Historian
9,825 Views
Registered: ‎02-25-2008


@alexejluft wrote:

And --- the amplitude is not really LVTTL like. I will test it on real hardware later.

 

The bandwith of the scope is only 50 MHz. So it could be that the scope shows a sine wave even though it's a square.


Yes. You want your 'scope and probe bandwidth to exceed the frequency of the signal by at least 5 times. Higher bandwidth is always better. A 50 MHz 'scope is a toy.

 

And an improper ground connection will also foul up the measurement.

----------------------------Yes, I do this for a living.
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