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11,944 Views
Registered: ‎03-08-2009

DCM - vrs - PLL

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Can somebody point me to some 'beginner or introductory' DCM data sheets or app notes?

 

I need to create a programable external "sampling clock" for a 16bit ADC that feeds into a spartan chip, in the range of 0..100mhz in some reasonable number of steps.

 

Many ARM soc chips have a PLL, that have a programable "DIV" and "MUL" value, that can thus reasonably generate numerous clock frequencies. I am quite familar with PLL style frequency generation.

 

On the surface, the DCM seems to be the FPGA version - but I don't understand it well, and/or I am confused by what I am reading. I am getting "lost in the woods" when reading the DCM data sheets. All of the DCM documentation I have found assumes you already know what a DCM is and how it works and how to configure it.

 

Can somebody point me to something, ie: "Chapter X.Y of Document ABC is a good intro/appnote/example/description of how to make a DCM work like a programable PLL"

 

Thanks.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

DLLs are pretty different than PLLs in many respects, e.g. they are built out of a series of digital delay taps, unlike a PLL.

 

You should generally start with the User Guide for your family, e.g.

http://www.xilinx.com/support/documentation/user_guides/ug331.pdf (Spartan-3 Generation FPGA User Guide)


Note that with the current families - you cannot change the multiple & divide values dynamically (except via the DRP port on Virtex-4 & Virtex-5).

 

This is a good introduction:

http://www.xilinx.com/support/documentation/application_notes/xapp462.pdf (Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs)

You also need to be aware of the specifications in the datasheet. There are limits on the input & output frequencies that depend on the family, programmed mode, configuration, etc.

 

bt

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Xilinx Employee
Xilinx Employee
13,953 Views
Registered: ‎08-13-2007

DLLs are pretty different than PLLs in many respects, e.g. they are built out of a series of digital delay taps, unlike a PLL.

 

You should generally start with the User Guide for your family, e.g.

http://www.xilinx.com/support/documentation/user_guides/ug331.pdf (Spartan-3 Generation FPGA User Guide)


Note that with the current families - you cannot change the multiple & divide values dynamically (except via the DRP port on Virtex-4 & Virtex-5).

 

This is a good introduction:

http://www.xilinx.com/support/documentation/application_notes/xapp462.pdf (Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs)

You also need to be aware of the specifications in the datasheet. There are limits on the input & output frequencies that depend on the family, programmed mode, configuration, etc.

 

bt

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11,913 Views
Registered: ‎03-08-2009

timpe>  This is a good introduction: http://www.xilinx.com/support/documentation/application_notes/xapp462.pdf

 

Thanks, that is exactly what I was looking for.

 

-Duane.

 

 

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Newbie
Newbie
10,365 Views
Registered: ‎10-26-2009

hi, i already try the dcm module, and i was reading also about the DDS.

i need to output frequencies depending of an input. 

 

and i need frequencies in the order of 76.65Mhz,  76.82Mhz,  76.99Mhz, 

how can i get this very small variations ???

 

 

thanks. 

 

 

 

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