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Newbie herp_baumer
Newbie
9,336 Views
Registered: ‎06-09-2009

DDR2 on Spartan-3E

I'm trying to build a DDR2 Memory Controller on a Spartan-3E Device. The MIG 3.0 seems to support DDR2 Controller generation. So in the EDK-flow, i can select my desired memory.

But when I'm building my system, I get an error that an iostandard has not been specified. (Every needed constraint should be set by the integrated MIG GUI Flow!??)


LIT:411 - IOBUFDS symbol
   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_s3_ddr2_phy.mpmc_phy_if_0/iobs/datapat
   h_iobs/gen_dqs[1].dqs_iob/dqs_no_sim.diff_dqs.iobuf_dqs" (output
   signal=DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_s3_ddr2_phy.mpmc_phy_if_0/dqs_in
   t_delay_in<1>) does not have IOSTANDARD specified.

 

What's wrong? Does MIG3.0 not realy support DDR2 for Spartan-3E devices?

 

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6 Replies
Xilinx Employee
Xilinx Employee
9,329 Views
Registered: ‎10-23-2007

Re: DDR2 on Spartan-3E

MIG does not support DDR2 with Spartan-3E (not sure about EDK).  I'm curious as to what you mean by "seems to support".

 

The issue with S3E is that it doesn't support SSTL18 class II which is the standard for DDR2.  However, if you have a design with short traces and a small number of components (1 or 2) you might find that class I is sufficient.  Do some IBIS simulations and see what you find.  I suspect it may be fine.

 

Good luck.

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Newbie herp_baumer
Newbie
9,301 Views
Registered: ‎06-09-2009

Re: DDR2 on Spartan-3E

MIG3.0 doesn't support DDR2 as a Core Generator plug-in. But in use wiht EDK, it's possible to insert a DDR2 Memory Controller. So i think, the correct constraints might be generated. Although i get this error message. 

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Observer drgrid
Observer
8,587 Views
Registered: ‎11-03-2009

Re: DDR2 on Spartan-3E

I too have a similar problem, and I hope to find an answer.  I am building a DDR2 controller for the Virtex 5.  I use the 

"integrated MIG GUI flow" as described in the MPMC document.  That document specifically states that MIG constraints

are passed into a core-level constraint file that is merged into the ISE tools during ngdbuild.  The EDK system.ucf 

file is NOT modified.

 

Yet I too get the ERROR:LIT:411 - IOBUFDS symbol error message, just as you have.  The output signal

name is slightly different, but it claims the IOSTANDARD is not specified.  In my case it is on the following

output signal:

 

   mpmc_0/mpmc_0/mpmc_0_core/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dqs[0].u_iob_dqs/dqs_ibuf

 

The documentation certainly gives the impression that with the Integrated MIG GUI flow for the MPMC, the MIG

constraints are merged into (some) core-level constraint file.  Is this not true?

 

Is there something in the documentation that I am missing?  Why doesn't this work? 

 

Any help or insights would be very much appreciated!

 

    -Matt 

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Contributor
Contributor
8,577 Views
Registered: ‎02-12-2009

Re: DDR2 on Spartan-3E

Matt,

 

I was having the same problem as you.  I'm developing a system using the PPC440 in a V5 device for the ML507 eval board.  I was encouraged by our FAE to use ISE to start the design, so I ran into this problem when attempting to implement the design from ISE.

 

I had to add the UCF from EDK to the ISE project ( Project - Add Source ).  That got me past that error.

 

DornerWorks
https://goo.gl/LNexn5



Xilinx Alliance Program - Premier Tier
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Observer drgrid
Observer
8,433 Views
Registered: ‎11-03-2009

Re: DDR2 on Spartan-3E

Kkoorndyk,

 

Thanks for taking the time to reply. Could you expand on your answer a bit?  Exactly which UCF from the EDK did you add

to the ISE project?  And when you added it to your ISE project, was it your top-level UCF in the ISE project?

 

Thanks,

Matt

 

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Adventurer
Adventurer
7,646 Views
Registered: ‎11-17-2009

Re: DDR2 on Spartan-3E

I have a same problem with virtex-5 when i include the xps as a subblock in ISE.

 

ERROR:LIT:411 - IOBUFDS symbol
   "VegaPc/DDR2_SDRAM_16Mx32/DDR2_SDRAM_16Mx32/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dqs[0].u_iob_dqs/gen_dqs_iob_ddr2.u_iobuf_dqs"
   (output
   signal=VegaPc/DDR2_SDRAM_16Mx32/DDR2_SDRAM_16Mx32/mpmc_core_0/gen_v5_ddr2_phy
   .mpmc_phy_if_0/u_phy_io_0/gen_dqs[0].u_iob_dqs/dqs_ibuf) does not have
   IOSTANDARD specified.

 

Can any body comment on this error?

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