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5,925 Views
Registered: ‎10-08-2014

ERROR:Pack:1107 - Pack was unable...

Dear All,

 

We have a problem about our project.

 

We have a Spartan 6 (XC6SLX75-2FGG484C) FPGA and we try to do some tests on our new board. In our top level we have only two blocks one of which generates some test patterns and the other block is a serializer which is for CameraLink outputs.

 

There is an LVDS oscillator outside the FPGA and we take the LVDS clock signals (clk1_p & clk1_n) from Bank 2 with an IBUFGDS (also tried with IBUFDS). Then, we sent the single ended clock (clk1) to the serializer block which includes a clock generator pll and some serdes transmitter blocks. clk1 is used inside the serializer and another single ended clock signal clk2 is generated by the pll and sent outside of this block to be used in our test pattern generator block. And the patterns generated are sent to the outside world by serializer block on Bank 0 and Bank 2 as LVDS cameralink signals. Our test is basically like this.

 

When we want to generate a bit file we get this error:

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a single IOBS component because the site type selected is not compatible.

 

Our LVDS clock is connected to a GCLK IO pair on Bank 2. 

Our cameralink_1 signals are connected to the pins on Bank 2.

Our cameralink_2 signals are connected to the pins on Bank 1.

 

We get these results like below when we try to generate bit stream with different ways:

 

1- LVDS clock + cameralink_1 signals on UCF:

ERROR:Place - ConstraintResolved NO placeable site for sb_serializer_block_0/sb_clock_generator_pll_s8_diff_0/tx_bufpll_inst
ERROR:Place - SIO has over-constrained componet sb_serializer_block_0/sb_clock_generator_pll_s8_diff_0/tx_bufpll_inst to have to placeable sites. Constraints come from driver constraints AND load IO constraints

 

2- cameralink_1 signals on UCF:

bit file generated (LVDS clock is placed to two GCLK pins on Bank 0 automatically)

 

3- cameralink_1 + cameralink_2 signals on UCF:

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a single IOBS component because the site type selected is not compatible. (12 times, I guess only for cameralink_2 signals)

 

The weird think is LVDS outputs cannot be mapped into Bank 0 as far as I understand up to now. However, in UG381, on page 28, it says that: 

LVDS inputs can be placed on any I/O bank, while LVDS outputs are only available on I/O banks 0 and 2.
 
I have LVDS clock input on Bank 2 and cameralink LVDS outputs on Bank 0 and Bank 2.
 
I hope I could be able to tell the situation.
 
How can we solve this problem? We need all ideas. Please help!
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Professor
Professor
5,902 Views
Registered: ‎08-14-2007

There should be more text to those error messages.  Can you attach the entire map report?  The map report file has a .mrp extension an should be in the project directory.

-- Gabor
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Registered: ‎10-08-2014


@gszakacs wrote:

There should be more text to those error messages.  Can you attach the entire map report?  The map report file has a .mrp extension an should be in the project directory.


@gszakacs First of all thank you very much for your interest. I copied one of the error message here and you can find the mrp document as attached.

 

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a single IOBS component because the site type selected is not compatible.

 

Further explanation:
The component type is determined by the types of logic and the properties and configuration of the logic it contains. In this case an IO component of type IOBS was chosen because the IO contains symbols and/or properties consistent with differential slave usage. Please double check that the types of logic elements and all of their relevant properties and configuration options are
compatible with the physical site type of the constraint. 

 

Summary:
Symbols involved:
PAD symbol "cl2_y_clk_n" (Pad Signal = cl2_y_clk_n)
SlaveBuffer symbol
"sb_serializer_block_0/sb_serdes_tx_4/sb_serdes_n_to_1_s8_diff_clock/loop0[0]
.io_clk_out/SLAVEBUF.DIFFOUT" (Output Signal = cl2_y_clk_n)
Component type involved: IOBS
Site Location involved: B16
Site Type involved: IOBM

 

 

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Xilinx Employee
Xilinx Employee
5,867 Views
Registered: ‎09-20-2012

Hi @isravisioncamera

 

It looks like you are using p-type package pin for n-type port and vice-versa.

 

B16 is p-type pin where as A16 is n-type pin. So use B16 for cl2_y_clk_p and A16 for cl2_y_clk_n.

Thanks,
Deepika.
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Highlighted
5,863 Views
Registered: ‎10-08-2014


@vemulad wrote:

Hi @isravisioncamera

 

It looks like you are using p-type package pin for n-type port and vice-versa.

 

B16 is p-type pin where as A16 is n-type pin. So use B16 for cl2_y_clk_p and A16 for cl2_y_clk_n.


@vemulad thank you very much for your idea but I think it is not our problem for this subject. As I wrote in my first message, without CL2 signals, ISE cannot map our clock signal on Bank 2 and all CL1 signals are correctly placed.

 

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Xilinx Employee
Xilinx Employee
5,817 Views
Registered: ‎08-01-2012

Please check whether the information in below answer records(AR) helpful to debug clues. Please note that the AR are meant for different version of tools and different devices. But some of core concepts are useful to check. 

http://www.xilinx.com/support/answers/25058.html

http://www.xilinx.com/support/answers/34270.html

http://www.xilinx.com/support/answers/47813.html

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