01-31-2010 01:17 AM
Hi, Guys
I've some trouble in the Post PAR simulate in the modelsim 6.3.
It's a very simple project, only include the DCM and counter, a piece of the source code is as below:
========================================================================
DCM_SP #(
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(20), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_SP_Double (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLK180(CLK180), // 180 degree DCM CLK output
.CLK270(CLK270), // 270 degree DCM CLK output
.CLK2X(clk_100m), // 2X DCM CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
.CLK90(CLK90), // 90 degree DCM CLK output
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM LOCK status output
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM status bits output
.CLKFB(CLKFB), // DCM clock feedback
.CLKIN(clk_50m), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(PSCLK), // Dynamic phase adjust clock input
.PSEN(PSEN), // Dynamic phase adjust enable input
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
.RST(rst) // DCM asynchronous reset input
);
BUFG DCM_BUFG_INST(
.I(CLK0),
.O(CLKFB)
);
========================================================================
The funtion simulation is OK, but when I come to the PAR simulation, the fatal error show up, the message is as below:
# do {clone_tb.tdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.5a Compiler 2009.03 Mar 27 2009
# -- Compiling module path_clone
#
# Top level modules:
# path_clone
# Model Technology ModelSim SE vlog 6.5a Compiler 2009.03 Mar 27 2009
# -- Compiling module clone_tb
#
# Top level modules:
# clone_tb
# Model Technology ModelSim SE vlog 6.5a Compiler 2009.03 Mar 27 2009
# -- Compiling module glbl
#
# Top level modules:
# glbl
# vsim -L simprims_ver -lib work -t 1ps +maxdelays clone_tb glbl
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: path_clone.v(84): Module 'DCM_SP' is not defined.
# ** Error: path_clone.v(89): Module 'BUFG' is not defined.
# Optimization failed
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./clone_tb.tdo PAUSED at line 9
vsim simprims_ver.X_DCM
# vsim simprims_ver.X_DCM
# ** Note: (vsim-3812) Design is being optimized...
# Loading simprims_ver.X_DCM(fast)
vsim simprims_ver.X_DCM_SP
# vsim simprims_ver.X_DCM_SP
# ** Note: (vsim-3812) Design is being optimized...
# Loading work.X_DCM_SP(fast)
========================================================================
I've compiled the lib and map into modelsim, so I don't know what make modelsim is unhappy ? :)
Can someone give me hand, thanks.