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Visitor afstkla
Visitor
5,920 Views
Registered: ‎10-18-2012

Errors: Latches and combinatorial loops

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Hi all,

 

I have got a school assignment to program an FPGA in such a way that it will give out a PWM signal (that is, differing Duty Cycles) according to whether the incoming frequency is higher or lower than 1kHz. I have built the verilog code that takes a frequency (right now it is still 10-bit input, I will later add the module for converting an incoming frequency to a 10bit number) and converts it to a Duty Cycle. It runs great in the simulator, but when I try to press 'Synthesize - XST', I get a few strange errors, which I hope you can help me solve.

 

I have the following code (part of the full code):

[code]

reg [9:0] DC; //Part 2: States -> DC
initial DC = 500;

always #500
case(sel)
7: begin
if(DC < 40) begin
DC[9:0]= 0;
end
else
begin
DC[9:0]= DC[9:0] - 40;
end
end
6: begin
if(DC < 10) begin
DC[9:0] = 0;
end
else
begin
DC[9:0] = DC[9:0] - 10;
end
end
5: begin
if(DC < 1) begin
DC[9:0] = 0;
end
else
begin
DC[9:0] = DC[9:0] - 1;
end
end
4: begin
DC[9:0] = DC[9:0];
end
3: begin
if(DC > 999) begin
DC[9:0] = 1000;
end
else
begin
DC[9:0] = DC[9:0] + 1;
end
end
2: begin
if(DC > 990) begin
DC[9:0] = 1000;
end
else
begin
DC[9:0] = DC[9:0] + 10;
end
end
1: begin
if(DC > 960) begin
DC[9:0] = 1000;
end
else
begin
DC[9:0] = DC[9:0] + 40;
end
end
0: begin
DC[9:0] = 500;
end
endcase[/code]

 

which checks if the next Duty Cycle should be changed, and if so, how much. (Duty cycle is, for precision purposes, calculated in promillage)

 

When I Synthesize this design, I get the error "Found 1-bit latch for signal <DC<x>>. (where x stands for one of the 10 bits of DC). Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPL designs, as they may lead to timing problems". I have absolutely no idea what I am missing in the code, because I think the case statement is complete, and all if statements have accompanying else statements.

 

In addition to that, I get the following, strange, warnings: "Unit NextDC (that is my project's name) : the following signal(s) form a combinatorial loop: Madd_n0113_lut<1>, PWM_out, (...)", and this list continues virtually forever. Most of the mentioned signals were produced by Xilinx, because I recognise only a few...

 

Thanks in advance!

 

Job

 

Attached is the complete program, which is indeed (probably) not nicely coded, but it has to work, not to be elegant... ;-)

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1 Solution

Accepted Solutions
Instructor
Instructor
7,963 Views
Registered: ‎08-14-2007

Re: Errors: Latches and combinatorial loops

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You are trying to use a delay to create timing:

 

always #500

 

The "#500" is ignored for synthesis (how do expect the hardware to create

a 500 ns delay?).  So in effect your entire loop runs "always."

 

You need to add a clock to make this run in hardware like:

 

always @ (posedge clk)

 

then you won't have latches or combinatorial loops.

 

-- Gabor

-- Gabor
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4 Replies
Instructor
Instructor
7,964 Views
Registered: ‎08-14-2007

Re: Errors: Latches and combinatorial loops

Jump to solution

You are trying to use a delay to create timing:

 

always #500

 

The "#500" is ignored for synthesis (how do expect the hardware to create

a 500 ns delay?).  So in effect your entire loop runs "always."

 

You need to add a clock to make this run in hardware like:

 

always @ (posedge clk)

 

then you won't have latches or combinatorial loops.

 

-- Gabor

-- Gabor
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Visitor afstkla
Visitor
5,896 Views
Registered: ‎10-18-2012

Re: Errors: Latches and combinatorial loops

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Aaah, I get it! Thanks a lot!

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Visitor afstkla
Visitor
5,887 Views
Registered: ‎10-18-2012

Re: Errors: Latches and combinatorial loops

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I have changed it in the program, and the latches errors went away. But right now I keep getting 'combinational loop' errors. What should I do to solve them?

 

I have added the refined code in the attachment

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Instructor
Instructor
5,871 Views
Registered: ‎08-14-2007

Re: Errors: Latches and combinatorial loops

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Your last process is still combinatorial.  It is "triggered" by its

inputs changing rather than a clock.  For synthesis this means

that it produces combinatorial logic rather than flip-flops.

 

For a combinatorial process, you should not have feedback within

the process or you create "combinatorial loops."  For example you

have written:

 

PWM_accumulator = PWM_accumulator + 1;

With nothing preventing from running constantly, this means you want to

continously increment your accumulator.  This should also happen in

a clocked process.  Alternately if you only have one signal that needs

feedback in an otherwise combinatorial process, you can place the feedback

register in a separate clocked process like:

 

reg [10:0]PWM_feedback;

always @ (posedge clk) PWM_feedback <= PWM_accumulator;

 

and in the combinatorial process:

 

PWM_accumulator = PWM_feedback + 1;

replacing PWM_accumulator with PWM_feedback on the right-hand side of all equations.

 

HTH,

Gabor

-- Gabor
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