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mechouk
Visitor
Visitor
4,291 Views
Registered: ‎05-19-2008

GTP PLL lock issue

Hi,

 

I use in my design the GTP Core generated by the Wizard. I use the four tiles using only the PLL0s, each tile is the same. I also used two user clocks (one for TX (lane speed: 0.64Gbps) and one for RX(1.28Gbps)). So I have 6 PLLs. My GTP design is completely symmetrical.

 

Only one PLL (PLL0) of the MGT_USRCLK block is locked, the other (PLL1) is locked for a short time, then is unlocked for another short time before being re-locked for a short time and so on....

 

For the tile PLLs, only the WEST PLLs is locked and the EAST PLLs have the same behavior than the MGT_USRCLK PLL1.

 

Does somebody have an idea why the behavior of the PLL is like that???? Maybe a solution ???

 

Thanks,

Regards,

Nicolas.

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Device : XC6SLX150T-2fgg676
SW : ISE 13.1 updated
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rcingham
Teacher
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Registered: ‎09-09-2010

Which device?
What software version?

And you would be more likely to get an answer posting in the "Connectivity" forum:
http://forums.xilinx.com/t5/Connectivity/bd-p/CONN

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"If it don't work in simulation, it won't work on the board."
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mechouk
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Registered: ‎05-19-2008

Sorry, I forgot them.... I will put them in my signature...

 

Device : XC6SLX150T-2fgg676

SW : ISE 13.1 updated

 

I don't think it's a connectivity issue but rather a S6 PLL issue, that why I post here.... :smileywink: but ok, I' m going to post it on the Connectivity Forum....

Nicolas.

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Device : XC6SLX150T-2fgg676
SW : ISE 13.1 updated
---------------------------------------------
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Anonymous
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4,176 Views

 
Did you ever get this one figured out?
 
I am seeing a very similar issue on the Same device and SW version.
 
Al... 
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