05-04-2011 02:59 AM - edited 05-04-2011 04:16 AM
I use in my design the GTP Core generated by the Wizard. I use the four tiles using only the PLL0s, each tile is the same. I also used two user clocks (one for TX (lane speed: 0.64Gbps) and one for RX(1.28Gbps)). So I have 6 PLLs. My GTP design is completely symmetrical.
Only one PLL (PLL0) of the MGT_USRCLK block is locked, the other (PLL1) is locked for a short time, then is unlocked for another short time before being re-locked for a short time and so on....
For the tile PLLs, only the WEST PLLs is locked and the EAST PLLs have the same behavior than the MGT_USRCLK PLL1.
Does somebody have an idea why the behavior of the PLL is like that???? Maybe a solution ???
05-04-2011 03:09 AM
05-04-2011 03:54 AM - edited 05-04-2011 04:15 AM
Sorry, I forgot them.... I will put them in my signature...
Device : XC6SLX150T-2fgg676
SW : ISE 13.1 updated
I don't think it's a connectivity issue but rather a S6 PLL issue, that why I post here.... :smileywink: but ok, I' m going to post it on the Connectivity Forum....