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Observer yuhui
Observer
4,311 Views
Registered: ‎06-03-2010

How to divide SPI Flash into 2 areas

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Hi,

  My FPGA board has a third party 128Mbit SPI Flash(Numonys M25P128), for now follow the the Xilinx Application Note: XAPP974 and configure it indirectly in iMPACT using JTAG tool, the whole chip is programmed. 

  I want to know if there's anyway to divide the Flash into 2 areas, 1st part is used for permanent information(Serie number, etc), 2nd part is used to store the bitstream file. I also want to build a bypass between the SPI Flash with DSP(embedded on the board which provides other function), so the DSP could get access to the 2nd part and program it (updating the bitstream).

  I don't know how to realize it, could anyone please help me? Thank you.

 

 

Gladys

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1 Solution

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Teacher eteam00
Teacher
5,448 Views
Registered: ‎07-21-2009

Re: How to divide SPI Flash into 2 areas

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The simplest means of programming the SPI flash with Impact is to create an image file for the 'permanent' upper half data, and (in Impact) merge this image file with the .bit file to build a whole-chip image file for programming.

 

Alternatively, it is possible (needs to be verified) that if the image file created in Impact covers only the lower half of the SPI flash memory, Impact will only erase and over-write the lower half of the flash memory (and leave the upper half content intact).  Hopefully an Impact guru can confirm or deny this possibility.

 

As for sharing access to the SPI flash memory between two masters (e.g. FPGA and DSP), there are a number of ways to do this.  Here's one:

 

Connect the DSP's SPI interface to the FPGA (4 signal lines), and inside the FPGA route these 4 signal lines directly to the FPGA's connections to the SPI flash memory.  After FPGA is configured, the DSP has immediate and direct access to the SPI memory.  Until the FPGA is programmed, the DSP is 'locked out'.  The downside of this scheme is you need a working FPGA config to update the stored FPGA config image -- this won't work for recovery from a 'no-go' FPGA config.

 

Here's a second approach:

 

DSP drives the FPGA PROG_B* input low, which tri-states the FPGA's SPI connections.  This allows the DSP to master the SPI memory.  The DSP will have to 'hi-Z' its SPI_CLK and SPI_MOSI lines when the PROG_B* line isn't driven low, so that the FPGA can configure.  After the FPGA is configured, the DSP and FPGA can work out any scheme you wish for managing (avoiding) SPI contention.

 

If you have multiple SPI drops or sources, you must pay careful attention to signal integrity issues.  Reflections on the SPI_CLK signal (at the SPI memory) would be fatal.  Ringing and reflections on the data lines are OK, up to a point.  If they take too long too settle, then once again the interface is compromised.  From a signal integrity standpoint, the safest approach is to route the SPI signals from the DSP through the FPGA (scheme #1 above).

 

I know that loading the FPGA config image at address 0 (and up) works for configuration.  I don't know that loading the FPGA config image elsewhere will work.  Maybe someone more knowledgeable can clear this up.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

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4 Replies
Teacher eteam00
Teacher
5,449 Views
Registered: ‎07-21-2009

Re: How to divide SPI Flash into 2 areas

Jump to solution

The simplest means of programming the SPI flash with Impact is to create an image file for the 'permanent' upper half data, and (in Impact) merge this image file with the .bit file to build a whole-chip image file for programming.

 

Alternatively, it is possible (needs to be verified) that if the image file created in Impact covers only the lower half of the SPI flash memory, Impact will only erase and over-write the lower half of the flash memory (and leave the upper half content intact).  Hopefully an Impact guru can confirm or deny this possibility.

 

As for sharing access to the SPI flash memory between two masters (e.g. FPGA and DSP), there are a number of ways to do this.  Here's one:

 

Connect the DSP's SPI interface to the FPGA (4 signal lines), and inside the FPGA route these 4 signal lines directly to the FPGA's connections to the SPI flash memory.  After FPGA is configured, the DSP has immediate and direct access to the SPI memory.  Until the FPGA is programmed, the DSP is 'locked out'.  The downside of this scheme is you need a working FPGA config to update the stored FPGA config image -- this won't work for recovery from a 'no-go' FPGA config.

 

Here's a second approach:

 

DSP drives the FPGA PROG_B* input low, which tri-states the FPGA's SPI connections.  This allows the DSP to master the SPI memory.  The DSP will have to 'hi-Z' its SPI_CLK and SPI_MOSI lines when the PROG_B* line isn't driven low, so that the FPGA can configure.  After the FPGA is configured, the DSP and FPGA can work out any scheme you wish for managing (avoiding) SPI contention.

 

If you have multiple SPI drops or sources, you must pay careful attention to signal integrity issues.  Reflections on the SPI_CLK signal (at the SPI memory) would be fatal.  Ringing and reflections on the data lines are OK, up to a point.  If they take too long too settle, then once again the interface is compromised.  From a signal integrity standpoint, the safest approach is to route the SPI signals from the DSP through the FPGA (scheme #1 above).

 

I know that loading the FPGA config image at address 0 (and up) works for configuration.  I don't know that loading the FPGA config image elsewhere will work.  Maybe someone more knowledgeable can clear this up.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

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3,862 Views
Registered: ‎07-18-2011

Re: How to divide SPI Flash into 2 areas

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I have a similar question.

I want to divide m25p16 to 2 parts. lower part is for fpga mcs file. higher part is a binary (fat file system). how can I write the SPI flash by impact  or how can i merge mcs and  the binary file?

please give me more detail guide.

Thank you very much.

Tags (1)
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Teacher eteam00
Teacher
3,853 Views
Registered: ‎07-21-2009

Re: How to divide SPI Flash into 2 areas

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@ jinpeterzhang

 

It is considered bad manners to ask such questions in private messages rather than posting in the forums,

and it is considered bad manners to post an unrelated question or topic to an existing thread.

 

Please start a new thread for your topic.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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3,849 Views
Registered: ‎07-18-2011

Re: How to divide SPI Flash into 2 areas

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sorry.

I will do it

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