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7,500 Views
Registered: ‎12-02-2011

How to output differential clock using Spartan3A 3s1400a ?

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My project output differential clock using Virtex5 LX110 properly,  Now I need rebuild this project using Spartan3A 1400A,

 

This is the code :

 

wire		TCLKI_Q;

OFDDRRSE OFDDRRSE_TCLKI (
.Q(TCLKI_Q), // Data output (connect directly to top-level port)
.C0(TCLK_G), // 0 degree clock input
.C1(~TCLK_G), // 180 degree clock input
.CE(1'b1), // Clock enable input
.D0(1'b0), // Posedge data input
.D1(1'b1), // Negedge data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous preset input
);

OBUFDS #(.IOSTANDARD("DEFAULT"))  OBUFDS_TCLKI ( .O(OHPP_TCLKI_P), .OB(OHPP_TCLKI_N), .I(TCLKI_Q) );

Process "Translate" completed successfully,

 When Running map...

 

ERROR:LIT:156 - The O pin of OBUF symbol "OFDDRRSE_TCLKI/OBUF1" (output
   signal=TCLKI_Q) does not have a valid load. It is driving: pin I of OBUFDS
   symbol "OBUFDS_TCLKI" (output signal=OHPP_TCLKI_N), pin SNK of Output PAD
   symbol "TCLKI_Q".
Errors found during logical drc.

 

I use the ISE 13.2 WIN32,

 

Every idea would be appreciated!  

 

Thank advance .

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1 Solution

Accepted Solutions
eteam00
Professor
Professor
9,615 Views
Registered: ‎07-21-2009
  • Suggest you use the ODDR2 primitive for the Spartan-3A, instead of the OFDDRRSE primitive.

You can access the official device primitives from within the ISE Navigator shell by clicking on the 'light bulb' icon.

 

  • Make sure your project target has been updated to the Spartan-3A device.
  • Make sure the output diff pair is LOCed to a diff pair set of package pins.
  • You might want to consider replacing the .IOSTANDARD("DEFAULT") with the intended IO standard (e.g. LVDS_25).

-- Bob Elkind

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7 Replies
eteam00
Professor
Professor
9,616 Views
Registered: ‎07-21-2009
  • Suggest you use the ODDR2 primitive for the Spartan-3A, instead of the OFDDRRSE primitive.

You can access the official device primitives from within the ISE Navigator shell by clicking on the 'light bulb' icon.

 

  • Make sure your project target has been updated to the Spartan-3A device.
  • Make sure the output diff pair is LOCed to a diff pair set of package pins.
  • You might want to consider replacing the .IOSTANDARD("DEFAULT") with the intended IO standard (e.g. LVDS_25).

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

gszakacs
Instructor
Instructor
7,491 Views
Registered: ‎08-14-2007
  • Suggest you use the ODDR2 primitive for the Spartan-3A, instead of the OFDDRRSE primitive.

 

This is a great suggestion.  The OFDDRRSE was a library element for Virtex 2, and it's admirable that

Xilinx still allows its use in newer architectures even though the tools no longer support V2.  Still

you're best off sticking with the library elements for the part you're using.

 

I think the actual problem is that the OFDDRRSE contains the OBUF as well as the DDR register,

so it's Q output wants to be a PAD signal and not the input of an OBUFDS.

 

-- Gabor

-- Gabor
eteam00
Professor
Professor
7,488 Views
Registered: ‎07-21-2009

The OFDDRRSE was a library element for Virtex 2

 

Virtex 2 ?   I don't think either of us was even born yet in the days of Virtex 2.  How did a V2 primitive make it into a V5 design, or a Spartan-3A design?

 

Perhaps the rest of the code set should be checked for outdated primitives which need to be purged.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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gszakacs
Instructor
Instructor
7,485 Views
Registered: ‎08-14-2007

OK, let's pretend we're not dinosaurs...:smileyhappy:

 

Anyway, here's a clue to the problem in the original code:

 

.Q(TCLKI_Q), // Data output (connect directly to top-level port)

 

Pretty much says that you can't add an OBUF after the Q output.

 

-- Gabor

-- Gabor
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7,465 Views
Registered: ‎12-02-2011

Thank   and   for your reply !

 

 

When I replace OFDDRRSE with ODDR2 ,

 

My project has a correct result .

 

The cause of  the problem is that I have instantiated the OFDDRRSE from the "Spartan-3 Libraries Guide for HDL
Designs",  it has been replaced with ODDR2 in Spartan3A .

 

Is that mean that the Spartan 3 /3E can't output differential clock using  DDR ?

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gszakacs
Instructor
Instructor
7,459 Views
Registered: ‎08-14-2007

Is that mean that the Spartan 3 /3E can't output differential clock using  DDR ?

 

The naming convention for I/O components has changed since Spartan 3.  In the old

convention, the "O" at the beginning of a library element indicated that the output buffer

(OBUF or OBUFT) was included in the library element.  For Spartan 3, you can have

a DDR output flop wihout the output buffer.  It's called FDDRRSE (without an "O" at the

beginning).  Presumably you could attach an OBUFDS to its Q output.

 

Another approach to differential clock outputs is to use two OFDDRRSE components

and drive each pin with a single-ended IO standard.  This is the way MIG outputs

the clock to emulate differential SSTL2_II.  This method would not be as useful for

LVDS where it would require an external resistor network to provide the correct output

signal swing.

 

From MIG 2.3 (DDR2 for Spartan 3):

 

 U_clk_i : FDDRRSE
    port map (
      Q => ddr2_clk_q,
      C0 => clk0,
      C1 => clk180,
      CE => vcc,
      D0 => vcc,
      D1 => gnd,
      R => gnd,
      S => gnd
      );

U_clk_i_b : FDDRRSE
  port map (
    Q => ddr2_clkb_q,
    C0 => clk0,
    C1 => clk180,
    CE => vcc,
    D0 => gnd,
    D1 => vcc,
    R => gnd,
    S => gnd
    );

r_inst : OBUF
    port map (
        I => ddr2_clk_q,
        O => ddr2_ck(0)
    );

r_b_inst : OBUF
    port map (
        I => ddr2_clkb_q,
        O => ddr2_ck_n(0)
    );

Each DDR flop uses the same clock inputs, but has it's D inputs tied in the

opposite configuration to create opposite output clock phases.  When placing

a pair in adjacent IOB's (an IOB differential pair), the clock rouing is common

so the skew is very low - probably as good as using one DDR flop and a

differential output buffer.

 

-- Gabor

-- Gabor
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7,434 Views
Registered: ‎12-02-2011

Thank you for your help !

 

It is a new and good idea for me .

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