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nposozvezdie
Observer
Observer
4,693 Views
Registered: ‎11-30-2010

Invert clocks at runtime: Spartan-6 and Spartan-3 are different?

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Hi!

 

I need to change polarity of input and/or output clock at runtime. This is due to different vendors randomly use both active rising or active falling edge of clocks at data+clock input and output interfaces, and my device must work with both (user-selectable) cases.

There is no problem to use small XOR2 (or MUX2 and inverter), since XC3164A epoch, up to Spartan-3. Please see example on attached picture.

But when i compile it for Spartan-6, massive errors arrives, include

 

"This design contains a global buffer instance, <XLXI_2>, driving the net, <XLXN_4>, that is driving the following (first 30) non-clock load pins. ........"

 

How i can do correct runtime-changeable inversion of input and output clock without ugly "CLOCK_DEDICATED_ROUTE = FALSE" workaround?

I have fully synchronous design (i strongly hope).

 

Thank you!

 

Screenshot from 2013-06-09 15:12:51.png
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1 Solution

Accepted Solutions
gszakacs
Professor
Professor
5,745 Views
Registered: ‎08-14-2007

You have two problems, one with using LUT-based inversion in the clock path, and another

driving a global clock out on a pin.  For Spartan 6, you cannot route a global clock directly

to an output buffer.  Instead use an ODDR2 to forward the clock.  You can get a programmable

inversion on the ODDR2 forwarded clock by inverting the D inputs.  For example for your

RXCLKOUT, you could Tie C0 to the globally buffered RXCLKIN, C1 to the same clock after

an inverter (note that inversion is a special case because it does not require a LUT, but

rather gets pushed into the flop).  Then the D0 input would be tied to NOT RXCLKOUT_PHASE,

and D1 to RXCLKOUT_PHASE.  In this configuration, the D0 input goes to the Q output

when the input clock rises, and the D1 input goes to the Q output when the input clock falls.

 

 

-- Gabor

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3 Replies
austin
Scholar
Scholar
4,682 Views
Registered: ‎02-27-2008

n,

 

You should use the BUFGMUX primitive to select a 0 degree, or 180 degree clock.  This will ensure that the tools cooperate with you.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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gszakacs
Professor
Professor
5,746 Views
Registered: ‎08-14-2007

You have two problems, one with using LUT-based inversion in the clock path, and another

driving a global clock out on a pin.  For Spartan 6, you cannot route a global clock directly

to an output buffer.  Instead use an ODDR2 to forward the clock.  You can get a programmable

inversion on the ODDR2 forwarded clock by inverting the D inputs.  For example for your

RXCLKOUT, you could Tie C0 to the globally buffered RXCLKIN, C1 to the same clock after

an inverter (note that inversion is a special case because it does not require a LUT, but

rather gets pushed into the flop).  Then the D0 input would be tied to NOT RXCLKOUT_PHASE,

and D1 to RXCLKOUT_PHASE.  In this configuration, the D0 input goes to the Q output

when the input clock rises, and the D1 input goes to the Q output when the input clock falls.

 

 

-- Gabor

View solution in original post

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nposozvezdie
Observer
Observer
4,623 Views
Registered: ‎11-30-2010

Hi!

BUFGMUX and ODDR2 are exactly what i need. Dear friends, thank you so much. I attach here what i finally get, this schematic compiles without warnings, and works, hope it is precisely correct now.

(PS. I also change ISE 13.4 to 14.4 due to 'trce' program crashes; i use Linux)

Thanks!

s6clocking-correct.png
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