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keentolearn
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Registered: ‎07-07-2015

LPDDR controller Example design throws size mismatch error

The example design in the LPDDR controller generated throws "Size mismatch in mixed language port association, verilog port Dq" and also in three other buses. Is there any setting to be done before running this simulation. Where are x16 , x32 etc set which are used in the parameters file ?

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keentolearn
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The batch file is working. But not when I try to run it manually from ISE

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vsrunga
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Registered: ‎07-11-2011

@keentolearn

 

Unless the hierarchy is correct I suspect if running the simulation through ISE works.

Please run create_ise.bat in example_design/par folder and then invoke test.xise.

Try running the simulation of test.xise and double the hierarchy , signal mapping and model instantiation with your own project

 

Hope this helps

 

-Vanitha

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vemulad
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Registered: ‎09-20-2012

Hi @keentolearn

 

Which version of ISE are you using?

 

Thanks,

Deepika.

Thanks,
Deepika.
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keentolearn
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Deepika, I am using version 14.7

 

Vanitha, the test.xise which was created uses Modelsim which I do not have. How can I make it work in ISIM in a manual mode ?

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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

@keentolearn, create_ise.bat is a batch file that create ISE project named test.xise. You can simulate using ISIM or modelsim. If you do not have modelsim, ISIM can be used.

 

Hope this helps

 

-Vanitha

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keentolearn
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Thanks Vanitha. I did create the ise and ran it in ISIM. And as expected it throws up the same errors. Now unless I solve this I cannot check the functionality of my own design :-(

 

I suspect there is some variable I need to set somewhere.

 

ERROR:HDLCompiler:918 - "D:/Xilinx/new_hamster_with_lpddr_not_working/lpddr_ov7670/ipcore_dir/new_lpddr_controller/example_design/par/../sim/functional/lpddr_model_c3.v" Line 103: Size mismatch in mixed language port association, verilog port Dq
ERROR:HDLCompiler:918 - "D:/Xilinx/new_hamster_with_lpddr_not_working/lpddr_ov7670/ipcore_dir/new_lpddr_controller/example_design/par/../sim/functional/lpddr_model_c3.v" Line 104: Size mismatch in mixed language port association, verilog port Dqs
ERROR:HDLCompiler:918 - "D:/Xilinx/new_hamster_with_lpddr_not_working/lpddr_ov7670/ipcore_dir/new_lpddr_controller/example_design/par/../sim/functional/lpddr_model_c3.v" Line 101: Size mismatch in mixed language port association, verilog port Addr
ERROR:HDLCompiler:918 - "D:/Xilinx/new_hamster_with_lpddr_not_working/lpddr_ov7670/ipcore_dir/new_lpddr_controller/example_design/par/../sim/functional/lpddr_model_c3.v" Line 105: Size mismatch in mixed language port association, verilog port Dm
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit sim_tb_top in library work failed

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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

@keentolearn, please upload your mig.prj and datasheet.txt so that I will try to replicate the issue at my end.

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keentolearn
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Attached

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vsrunga
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Registered: ‎07-11-2011

@keentolearn

It looks the errors are due to Project Navigator trying to use the verilog behavioral models for simulating the VHDL IP core.

As a result the generic settings are not resolved correctly and the  mismatch is reported. 

 

To workaround the issue, generate the verilog version of the IP core and see how it goes

 

-Vanitha

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keentolearn
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Same errors with Verilog core as well

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keentolearn
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Any suggestions to solve this issue ?

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alanbrennan
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Registered: ‎12-14-2011

What's up?! Was working through similar problem today and I think I have a work around for this. Since you aren't making any reference to the generics x16, x512Mb etc in your code anywhere, you can hardcode them into the top of lpddr_model_parameters_c3.v

 

Like this:

 

`define x16
`define x512Mb
`define sg5

 

Otherwise you'll just default to the last entry in each 'ifdef. Which is why your port widths are all wrong. Double check the port widths in your component against the ones in this file with the settings you choose. I'm pretty sure that'll get you up and running. 

 

Hope it helps.

 

Al B.

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