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Newbie
Newbie
6,401 Views
Registered: ‎06-05-2014

Layout Spartan 6 CSG484

Hi

 

I am working on a layout with a  XC6SLX100-3CSG484C. I´m using  a 6 layers board (4 signal layers and 2 internal planes). I´ve problems to fanout this package because i need access to a lot of  package pins in the escape pattern 

Im working with a PCB mananufacturer that allowme to use Clearance: 5 Mils, Width: 4 Mils, Via diameter 18Mils,Via Hole size: 8Mils, and Minimum Annular Ring 5Mils but not less and this is a problem

 

Wich parameters for manufacturing do you recomend to use in this package? Do you recomend any manufacturer in US with web service for this kind of project? Do i´ve to use blind or buried vias?

 

 

Thanks.

 

Dario

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Professor
Professor
6,399 Views
Registered: ‎08-14-2007

Re: Layout Spartan 6 CSG484

Given the design rules, you can only route one signal between vias.  This means you either need to go to more layers or find a board house with tighter design rules.  Which way you choose to go may depend on the relative cost of layers vs high-density design rules.  Are you very space-constrained or could you consider increasing the board area a little to use the FGG484 instead of the CSG484?

 

Some things that cost money but could increase the routes you get per layer:

 

smaller minimum width / spacing

blind vias

laser drilling

 

In my designs using similar packages, I typically have a 12 layer board with 4 plane layers and 8 routing layers and 4 mil minimum trace width and spacing, at least on inner layers.

-- Gabor
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Xilinx Employee
Xilinx Employee
6,377 Views
Registered: ‎08-01-2012

Re: Layout Spartan 6 CSG484

In your case I think either you have to increase number of PCB layers or reduce the number of IO connections in design is one of the solution.  

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Instructor
Instructor
6,373 Views
Registered: ‎07-21-2009

Re: Layout Spartan 6 CSG484

In your case I think either you have to increase number of PCB layers or reduce the number of IO connections in design is only the solution.

 

I respectfully disagree.  Increasing layer count reaches diminishing returns if vias block routing channels (on all layers).

 

Most likely the least expensive solution is to tighten up the design rules to permit 2 traces between vias in the escape pattern.  5mil / 4mil design rules might be OK for 1mm pitch BGAs, but not for 0.8mm pitch BGAs.  4/4 design rules should allow 2 traces between vias (inner layers) and 1 trace between pads (component layer).

 

There will be a board fab upcharge for tighter design rules, but the overall board cost difference is usually minor.  For some designs, 5/5 design rules can be used everywhere in the board design except at the FPGA and the DRAM, where traces (and spacing) need to be necked down.  Sometimes a board fab house will waive the design rules upcharge if the use of the tighter rules is limited (for example, limited to escape patterns for DRAM and FPGA).

 

Gabor's advice is spot on.

 

-- Bob Elkind

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Xilinx Employee
Xilinx Employee
6,335 Views
Registered: ‎08-01-2012

Re: Layout Spartan 6 CSG484

I respect the  Bob Elkind comments. 

 

Also the following link http://www.xilinx.com/support/documentation/user_guides/ug393.pdf "Table A-3: Recommended PCB Design Rules (mm) for CSP Packages"  information is useful for cross checking while doing PCB layout. 

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