02-10-2014 03:00 PM
I'm just getting started on a MCB design interfacing to a DDR3 memory. I've configured and run the MIG tool to generate an example design to test/simulate with. I'm examining the sim_tb_top.v testbench file and it's simulated waveforms in order to get a better handle of the user interface signals, but I'm confused by the lack of clock transitions on either design_top.c3_p0_cmd_clk, design_top.c3_p0_wr_clk, or design_top.c3_p0_rd_clk - they remain at HiZ the entire simulation.
While I'm able to inspect the other signal waveforms for reference, it is confusing to see no driving clock signals for the memory port FIFOs (cmd,wr, and rd). Can anyone help explain this?
02-10-2014 04:04 PM
C3_px_cmd_clk, wr_/rd_clk are user inputs so you have to map those ports to proper frequency.
Are you simulating MIG example design and not seeing them or it is user deisgn?
Please refer UG388 MCB functional description and MCB operation chapter for more details.
Also go through below Xilinx AR and try flow1
Hope this helps
02-11-2014 11:35 AM
Thank you for your response. AR#37424 seems to address generating and implementing a MIG design; however, I'm just working in simulation while I'm waiting for my SP605 eval board to ship.
The waveforms depicted in my original post are of the example design. I've just re-generated the MIG design using coregen, and the example design's simulation still doesn't show a logical 1 or 0 for these 3 clk signals (cmd_, wr_, and rd_). This issueis more of a curiousity than a show-stopper, but I wish I knew why these signals are held at HiZ.
02-11-2014 04:15 PM
If this is example design simulation I expect the clocks to toggle but the simulation flow is also same as the implementation given in AR37424 except that you have to run example_design/sim folder do sim.do
If you followed the same way and can't see the clocks please upload your mig.prj and example_top.ucf for further inputs.
Is this in 14.7 only or older versions?