Hi I am working on a clock generator module. The clocks that I want to genearte requires two DCMs cascaded. I have used a PLL in between them to reduce the jitter from the first DCM. The design works correctly during the behavioural simulation but only see the clocks from the first DCM and rest of the design is dead when I run a post translate simulation...
I get no errors. I get warnings during translate but it seems these warnings could be ignored... NgdBuild:1440, 1212,1211
I cant understand if this is a tool issue or am I not allowed to configure the DCM and PLL in this fashion....
Please help.
