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Visitor jsmith45
Registered: ‎05-05-2016

ODDR with different clock periods

The spartan 3E ODDR2 component is normally used with either a single clock, and its inverse, or with two different phase offsets of the same clock.


But is the component guarenteed to work "correctly" if the two clock inputs do not have the same period, as long as the clocking edges never coincide, and never get close enough that violating any setup time of the components in "" would be a concern?



Without going into design details, I have a situation where I have two phase aligned clocks from a DCM, one with double the period of the other, both with 50% duty cycle and with positive edges aligned. I have instanciated an OODR2 with DDR_ALIGNMENT="NONE". If I clock the ODDR2 with posedge of the slower clock, and negedge of the doubled clock (which will never occur at the same time, since they are positive edge aligned), a simulation seems to show that what I get is is basically a quadruple data rate ouput (relative to the slow clock), where the second and third output value are always the same. I suppose one could call it a modified triple data rate.  As strange as it sounds that is indeed the behavior I desire, but since this is definately not the intended use-case, I'm not 100% sure that the simulation is accurate here. 


Does anybody have any exprience with this or similar misuses of the ODDR2 component to confirm that this will work?




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Registered: ‎02-16-2010

Re: ODDR with different clock periods

You could simulate and check the design.
Don't forget to reply, give kudo and accept as solution
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