04-27-2016 01:10 PM
Hi, it's my first time working with a FPGA and I have a problem with I/O Constraints.
I have an external clock that oscillates at 10 MHz and I want to make a counter that will pulse every second.
I'm currently working on a DLP-FPGA wich have a Xilinx Spartan 3E XC3S250E -4TQ144 on it.
Here's the datasheet of it : DLP-FPGA DataSheet
I'm working with ISE Design Suite 14.7 and Xilinx PlanAhead 14.7 and coding in VHDL.
I use BitLoadApp to implement the bit file to SPI Flash.
Working on Window 7.
Counter Behavior :
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Counter is Port ( Clock_I : in STD_LOGIC; Clock_O : out STD_LOGIC); end Counter; architecture Behavioral of Counter is -- Input clock is 10 MHz -> 10^7 Hz signal signal_count : STD_LOGIC_VECTOR(23 DOWNTO 0); -- 10^7 Hz -> 24 bits begin CounterProcess: process(Clock_I) begin if Clock_I'EVENT AND Clock_I = '1' then if signal_count > 10000000 then signal_count <= (OTHERS => '0'); -- Reset counter else signal_count <= signal_count + 1; -- Increment end if; if signal_count < 5000000 then -- Half clock time - > 5 * 10^6 Clock_O <= '0'; else Clock_O <= '1'; end if; end if; end process CounterProcess; end Behavioral;
User Constraints UCF :
NET "Clock_I" LOC = P58; NET "Clock_O" LOC = P59;
P58 is P2 on DLP-FPGA.
P59 is P4 on DLP-FPGA.
Both are I/O.
See Table 1 of DLP-FPGA DataSheet.
The problem is that it seem like nothing happen.
The DLP-FPGA only receives the current and pass it to all other ports.
For example, if I connect the external clock to DLP-FPGA Pin 2
and connect DLP-FPGA Pin 4 to a LED, the LED should flash every second but it ain't.
And if I connect the LED to any other port, same thing happen.
I've checked with an oscillator detector to see if maybe the LED was flashing too quickly to be perceive,
but nothing, only constant current. I don't know if the external clock is too fast for the device
or if there's a problem with my code or user constraints.
Hope that you guys could help me, sorry for poor english.
04-27-2016 01:30 PM
Have you looked through the reports? Warnings? Errors? Timing?
A couple of suggestions: use an IBUFG for the input clock. Placing the clock on a global clock tree is required for a synchrnous design that meets timing and is robust. Make sure you have a period constrain for the clock, too.
Remember that the VHDL executes every statement all at the same time (it is hardware, not software). Look at you code, and consider what happens when all statements execute at the clock event and clock=1. Does it still make sense?
Here is my 24 bit counter:
always@(posedge sysclk) /*Clk300MHz)*/ begin
if (reset) begin
counter2 <= 24'b0; /* set all 24 bits = 0 */
counter2 <= counter2 +1; /* count */
04-28-2016 03:26 AM
Are you convinced that the FPGA is being configured and remains configured? It looks like the DONE pin on your board is connected to a green LED so is that turning on and staying turned on?
Just to prove that you can create your own design, specify the correct FPGA pins and connect to the correct pins on your board it would be good to build a VERY simple design that just connects one pin directly through to the other.
Clock_O <= Clock_I;
With that design configured into the device can you make your external LED connected to ‘Clock_O’ (P2) turn on and off by providing High or Low inputs to ‘Clock_I’ (P4)?
If that works then connect your 10MHz oscillator to ‘Clock_I’ (P4) and again the LED should appear to turn on but maybe not quite so brightly (as it is flashing really quickly!). Does that happen?
With any luck those experiments will have revealed your issue. There’s not anything obviously wrong with your HDL code. A classic technique used to generate a square wave is always to end with a divide by 2 stage. As such, your design would be improved by implementing a divide by 5,000,000 stage flowed by a divide by 2 stage. It is a good learning exercise to implement this synchronously; the divide by 5,000,000 stage should be used to enable the divide by 2 stage rather than generating a 2Hz clock signal (i.e. all logic would still be clocked at 10MHz). Also, to be really precise, your counter should take into consideration that it spends one clock cycle at zero; as such the test condition should be ‘if signal_count = 4,999,999 then’. Your code now would require ‘signal_count’ to reach 10,000,001 before being reset resulting in a division by 10,000,002 cycles.