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3,526 Views
Registered: ‎03-09-2010

Question about block ram FIFO reset

In my project, I have used block ram Fifo IP core having both independent read and write clocks.

During the asynchronous FIFO reset it writes 3 to 4 words in FIFO which shifts my write pointer.

can anybody give me the solution of this problem. I want to know whether FIFO reset depends upon

write CLk frequency.   

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Observer perica
Observer
3,462 Views
Registered: ‎05-18-2008

Re: Question about block ram FIFO reset

When nobody wants to answer you let me do it.

During generation of fifo you can choose couple of options for reset(s) signal.

When you generate fifo in core generator choose independent reset for read end write side, then in HDL (VHDL or verilog) connect it together.

 

Petar

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