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Visitor
Visitor
5,970 Views
Registered: ‎11-01-2011

RTL signal problem

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Hi, I am writing an up/down counter in vhdl.It is correct when I simulated behaviorally but RTL schematic seems wrong.

It seems that no signals connect to the counter(m_buf1 in the figure).Why did it happen? 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter8 is
    Port ( data : inout  STD_LOGIC_VECTOR (7 downto 0);
           reset : in  STD_LOGIC;
           en : in  STD_LOGIC;
           load : in  STD_LOGIC;
           up : in  bit;
           clk : in  STD_LOGIC);
end counter8;

architecture Behavioral of counter8 is
signal m_buf:std_logic_vector(7 downto 0):="00000000";
begin
process(clk,reset)
begin
if reset='0' then --reset the counter
	m_buf<="00000000";
	elsif (clk'event and clk='1' ) then --rising edge
	  if load='0' then
		  m_buf<=data;--load data
		else --enable the counter
		  if up='1' then
		    m_buf<=m_buf+1;
		  else
		    m_buf<=m_buf-1;
		  end if;
	  end if;
		
end if;
end process;
process(m_buf,load)
  begin
	if(load='1') then---
	data<=m_buf;
	else
	data<="ZZZZZZZZ";
	end if;
  end process;
end Behavioral;

 


RTL

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Teacher
Teacher
7,612 Views
Registered: ‎08-14-2007

Hi,

because the RTL-Viewer is overoptimizing the schematic, and thus not all connections are shown.

It's a common problem you find in a number of threads.

It's annoying, but simply ignore the RTL view.

As for now this tool is more confusing than helpful for beginners.

Better take a look at the synthesis report for informations about the synthesized hardware.

 

If your simulation runs well, everything is fine.

 

Have a nice synthesis.

  eilert

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Teacher
Teacher
7,613 Views
Registered: ‎08-14-2007

Hi,

because the RTL-Viewer is overoptimizing the schematic, and thus not all connections are shown.

It's a common problem you find in a number of threads.

It's annoying, but simply ignore the RTL view.

As for now this tool is more confusing than helpful for beginners.

Better take a look at the synthesis report for informations about the synthesized hardware.

 

If your simulation runs well, everything is fine.

 

Have a nice synthesis.

  eilert

View solution in original post

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Instructor
Instructor
5,965 Views
Registered: ‎07-21-2009

It's annoying, but simply ignore the RTL view.

 

I've read suggestions in these forums that the technology view (rather than the RTL view) is more useful.  Any difference in the technology view schematic?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor
Visitor
5,958 Views
Registered: ‎11-01-2011

Thank you for your answer.

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Teacher
Teacher
5,941 Views
Registered: ‎08-14-2007

Hi Bob,

confirmed, the Technology view creates a proper schemetic with all connections in it.

But since it only shows you a bunch of LUTs and FFs it does not provide the informations you want to see in the RTL view.

 

The first versions of the RTL viewer worked quite good, maybe the Xilinx programmers should roll back their repositories to these versions and start over.

 

Kind Regards

  Eilert

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