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Visitor bouthouri
Registered: ‎02-28-2010

Realization of frequency_counter with FPGA SPARTAN 3E

I' am a student who is realizing a frequency counter was based FPGA, I have a Spartan-3E Starter Kit I found difficulty in creating the VHDL code and the steps ...especially as I have to convert the input signal (analog) to digital using ADC present in the development kit....

Is it feasible that the above measurement range is from 1Hz to 50 MHz ????


please help me and thank you in advance ..

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Visitor bouthouri
Registered: ‎02-28-2010

Re: Realization of frequency_counter with FPGA SPARTAN 3E

I am a student enthusiasm to achieve a frequency-based FPGA using a development kit Spartan-3E .. At first I must create a VHDL code that describes the method for calculating the frequency ..

I think that: (1) I must first create one CLK1 clock frequency divider with carry on the oscillator clk = 5OMhz present in the SDK: CLK1 goes after 1s (the counting window)

(2) Then I do a detector head up or down (counter) that will contain the output frequency in Hz = nb simultaneously detect for 1s disposed of CLK1.

(3) Then, I must save this value in a flip-flop latch .....

(4) Finally the show first in the LCD display in the present kit developement, and secondly to the PC using the RS232 communication .....
Does this method is correct?
how to describe it in VHDL (just where I have to start ..)
Or I can use the ROM and microprocessor "softcore" (pico blaze or MicroBlaze) in this project and how??

Please help me find a solution or direct me because I feel very far for this project .. And thank you in advance
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Registered: ‎07-27-2009

Re: Realization of frequency_counter with FPGA SPARTAN 3E



Try to manage your 'project'. This is actually 3 subprojects: the counter design, the LCD interface design and the RS232 interface design. These subprojects have increasing complexity.


Start with the counter. Design the VHDL, simulate it in a simulator and next try to map it to the Xilinx board. You can use Xilinx Chipscope to provide virtual inputs and outputs to your counter module.


The LCD and RS232 follow the same project template: design, simulation, design fixing, simulation, ..., design mapping.


Using a softcore could be a big step as you will also have to master compilers, linkers, boot, ... This is probably the nicest way to get an impressive homework project but it also has the potential for a lot of frustration. Take it easy at first.



Note: use a version control system such as SVN or GIT to keep track of your modifications and efforts so at least you don't have to spend time figuring out why it worked yesterday night and not today ;-)





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Registered: ‎03-29-2010

Re: Realization of frequency_counter with FPGA SPARTAN 3E



I have just completed a design that is very similar to what you are trying to achieve.


My advice would be to get hold of Xilinx development board (you have) and using the ISE build the Microblaze core system.

It will put in the RS2323 hardware and i believe an LCD drive.

This is quite straight forward, and you should be up and running within a short space of time.


Regarding the VHDL, if you are new to this (or Verilog) that could take some time to get to grips with.

Secondly, there are quite a few device specific commands you will need to understand to make the design work.


If you more familiar with schematic entry, you might find that easier, and there are some easy to learn counters etc.


Regarding your frequency range, if you don't use an ADC and 'square' the signal using an LVDS/LVPECL buffer

you can expect to see input frequencies on Spartan-3AN, out past 230MHz!!


If you do get stuck, i can supply you with some VHDL sample code to get you going?

You certainly have a challenge!!!




Pat H



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Registered: ‎04-24-2014

Re: Realization of frequency_counter with FPGA SPARTAN 3E

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