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fpga_asic
Newbie
Newbie
6,981 Views
Registered: ‎06-29-2009

SPartan 3A clock synchronization with an other spartan 3A (same component)

Hello,

For a project, I need to be able to synchronize two FPGA (SPARTAN 3A-400) each other. They are fed by two XTALs (50 MHz )  which are roughly equal except a drift of 50 ppm. The basic idea is to synchronize two designs which are embedded by the two FPGAs.

 

In order to perform output signals correlation, I need to synchronize those two FPGA. Except a handshake base protocol, I must say I have no idea how to synchronize them.

 

Does anybody have a clue?

 

Thanks for your reply,

 

Mitch

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4 Replies
jprovidenza
Voyager
Voyager
6,963 Views
Registered: ‎08-30-2007

Why not designate one of them as the "master" and have him forward the 50MHz clock to the

other FPGA?  Then they both run on the exact same clock.

 

 

John Providenza

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fpga_asic
Newbie
Newbie
6,952 Views
Registered: ‎06-29-2009

Hello John!

I am thankfull for your reply!

Anyway that is not so simple....Due to SAFETY constraints I cannot used a global clock to feed the two FPGAs. Hardware was thus designed in that way : two FPGAs with their own 50 MHZ xtal (+/- 50 ppm).

Each FPGA implements an identical safety function and needs to have its output synchronized with the output coming from the other FPGA....

 

Any clue?

Thanks in advance!

Mitch

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jprovidenza
Voyager
Voyager
6,948 Views
Registered: ‎08-30-2007

How precisely do the outputs have to match?  Within 10ns?  5ns? ???

 

Clearly, the two clocks have potential to drift over time such that you might

slip by one or more clock cycles eventually.

 

If you are allowed to forward clocks between the 2 FPGAs, you could take

your 50MHz, up shift it to a much higher frequency using a DCM, then implement

a state machine to create a 50Mhz clock that is phase locked to the other FPGA.

 

If the other FPGA's clock is out of spec, the state machine would ignore it and generate

a 50MHz clock based sloely on it's own 50MHz.

 

John Providenza

 

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andrewmulcock
Visitor
Visitor
6,900 Views
Registered: ‎09-02-2007

Done similar to jprovidenza's idea before. works well.  One FPGA is master,  slave uses it's dcm to lock to master. Slave turns on when master is dead.

 

Alternatives:

 To PLL the second fpga to the first, I've used an external VCXO for this before.

  

 

Problem with two fpga's, If it's a safty critical system, then two FPGA's are not good enough, as which one is 'wrong' can not be determined. You need at least three to detect the 'odd one out'. 

 

Best you can do with two FPGA's is if both are not the same, then disable and reset. 

  you need to decide if you want to reset and try again , or disable, reset and wait for 'another input' to try again. i.e. some one pressing a button. With reset and try again, you can end up with a very slow speed multi vibrator, which you might not want.

 

How to answer 'are both outputs the same' is an interesting question.

  solutions range from having a 'keep alive' on each kicking the other, to a 'wait'  and 'handshake'. 

 

Advise is to keep safty system system simpl, so you can easily fully define all the stats it can get into.

 

 

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