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luismerca
Newbie
Newbie
3,378 Views
Registered: ‎03-29-2011

STD_LOGIC_VECTOR inout with just some bits of input type and others of output type

Hi! I'm using a spartan-3 development board and I want to use a STD_LOGIC_VECTOR like inout type but I don't want to use a tristate buffer, i already used this with sucess but what I want to do is using just 1 bit of the vector like output and the rest like outputs. Somebody can say if it is possible? and how can i do that?

 

Tank you

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rcingham
Teacher
Teacher
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Registered: ‎09-09-2010

You should be able to make it work in simulation, but I would bet heavy odds that it will cause XST and other synthesis tools to barf!

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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gszakacs
Instructor
Instructor
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Registered: ‎08-14-2007

Actually I think this is O.K. if I understand what you're asking.  For example in one

of my designs I have 5 signals that connect to a CPLD called CPLD_SIG(5 downto 1)

where some of the signals are inputs, others outputs, and yet others are bidirectional.

The port is defined as inout, but there is no code to drive the input-only pins and no

code that uses the output-only pins.  You do get warnings about unused paths, but this

will not cause errors in the build.  The only other approach is to re-name the signals

because it is not legal for parts of a vector port to have a different type or direction than other

parts of the same vector.

 

-- Gabor

-- Gabor
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bassman59
Historian
Historian
3,358 Views
Registered: ‎02-25-2008

 


@luismerca wrote:

Hi! I'm using a spartan-3 development board and I want to use a STD_LOGIC_VECTOR like inout type but I don't want to use a tristate buffer, i already used this with sucess but what I want to do is using just 1 bit of the vector like output and the rest like outputs. Somebody can say if it is possible? and how can i do that?

 

Tank you


 

You are making things WAAAY too complicated.

Declare the ports as inputs or outputs as necessary. There's no reason to combine them all into one std_logic_vector.

----------------------------Yes, I do this for a living.
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