UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
7,554 Views
Registered: ‎09-12-2011

Setup Timing Error in Spartan 6 design using ISE 14.6

Jump to solution

Dear Members;

 

 I have a setup timing error for a 16-bit data input with its clock. These are both inputs to the FPGA, directly connecting to the pins. I am using ISE 14.6 and targetting spartan lx150.

 

The clock is called PPort_Clk, goes through ibug->dcm -> bufg.

The data is called PPort_Data (16 bits wide).

 

The clock and offset in constraints I use are 

TIMESPEC TS_hp_ioclk_vsoc = PERIOD "PPort_Clk" 10 ns HIGH 50 %;

OFFSET = IN 5 ns VALID 10 ns BEFORE "PPort_Clk" RISING;

 

I receive setup errors and I am attaching the screen shot for one of them. 

According to the timing result, I can see clock goes through ibufg->dcm->bufg as I intended. And its delay is reasonable. 

 

However when I look at the data path delay, the delay is significant between the ibuf to the SRLC, 6.155ns. And the reason for this is mainly the location of the pin. You can see it from the arrow in the floorplan.png (attached).

 

Therefore I decided that the data path delay is significantly larger than the clock path delay, therefore I get the setup timing error. And I am not sure if this can be solved with smart explorer and high effort place & route, but I think I should be able to figure this out in other means.

 

Then I thought the logical way to correct this would be to delay the incoming clock. Please correct me if I am wrong here.

First I thought about adding IBUF_DELAY_VALUE but learned that this constraint can be applied to any input or bidirectional signal that is not directly driving a clock or IOB (Input Output Block) register. Then I figured I need to use “IFD_DELAY_VALUE” constraint for the constraint of signals driving clock and IOB registers.

 

The values I put in this delay value didn't change any of the clock delay. 

 

Then I tried adding delay to the ibufg for the clock:

EXT_CLK_IBUFG_INST: ibufg
generic map (ibuf_delay_value => "0",
ioStandard => "LVCMOS33")
port map (o => PPort_Clk_ibuf,
                    i => PPort_clk_in);

These didn't change any of the timing errors or the relevant delay.

 

I guess one other thing I can try would be to add IDELAYs.

 

Anyways I think I am in need to some recommendations where and how to proceed.

 

Any input is appreciated,

 

Regards, 

 

 

Tags (1)
timing_error.png
floorplan.png
0 Kudos
1 Solution

Accepted Solutions
Historian
Historian
9,969 Views
Registered: ‎01-23-2009

Re: Setup Timing Error in Spartan 6 design using ISE 14.6

Jump to solution

You need to get the tool NOT to infer the SRL, but instead to use two distinct FFs for each bit. The first one should then be placed in the IOB, and the second one can go elsewhere.

 

One easy way to do this is to add a reset to the flip-flops - SRLs cannot be reset, so if you code a reset, it will force the tool to use flip-flops. There is probably a synthesis directive that you could embed in your code to force it not to use an SRL for that flip-flop (but I don't remember what it is), and you can also turn of SRL inference globally in the synthesis options, but it may just be easier to add the reset...

 

Once you force the tools to give you FFs, and the first FFs gets put in the IOBs, this will meet timing easily.

 

Avrum

0 Kudos
9 Replies
Instructor
Instructor
7,549 Views
Registered: ‎08-14-2007

Re: Setup Timing Error in Spartan 6 design using ISE 14.6

Jump to solution

One possible thing to try is to place the SRL16 nearer to the input pin.  However that begs the question "why didn't the tools do that?"  I suspect that it was placed where it is in order to meet a PERIOD spec inside the FPGA.  My suggestion would be to replace at least the first stage of the SRL16 with either a fabric or IOB flop.  In fact depending on the minimum delay you need through the SRL16 you could add more flops up front to give the placement more leeway to meet both the input offset and PERIOD specs.

-- Gabor
0 Kudos
Teacher muzaffer
Teacher
7,547 Views
Registered: ‎03-31-2012

Re: Setup Timing Error in Spartan 6 design using ISE 14.6

Jump to solution
You can try to get the register to be in the IO by setting IOB constraint to true. This should help with the 6ns+ net delay. Also are you instantiating the DCM in the clock path? You can change the output phase of that too.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Explorer
Explorer
7,537 Views
Registered: ‎09-12-2011

Re: Setup Timing Error in Spartan 6 design using ISE 14.6

Jump to solution

Hello Muzaffer;

 

 I tried both of your recommendations, 

 

IOB Constraints for changed to :

INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_6" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_0" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_1" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_2" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_3" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_4" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_5" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_7" IOB =TRUE;

INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_8" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_9" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_10" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_11" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_12" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_13" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_14" IOB =TRUE;
INST "Inst_PPort_Receiver/Mshreg_PP_Data_In_Reg_2_15" IOB =TRUE;

 

This didn't change anything in terms of timing. 

 

I also tried to change the change the phase of the dcm as follows:

DCM_SP_inst : DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- CLKDV divide value
-- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32)
CLKFX_MULTIPLY => 4, -- Multiply value on CLKFX outputs - M - (2-32)
CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
CLKIN_PERIOD => PP_input_freq, -- Input clock period specified in nS
CLKOUT_PHASE_SHIFT => "FIXED", -- Output phase shift (NONE, FIXED, VARIABLE)
CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X)
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DSS_MODE => "NONE", -- Unsupported - Do not change value
DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
FACTORY_JF => X"c080", -- Unsupported - Do not change value
PHASE_SHIFT => 160, -- Amount of fixed phase shift (-255 to 255)
STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
port map (
CLK0 => PPort_Clk_dcm, -- 1-bit output: 0 degree clock output
-- Clocks below are not used
CLK180 => open, -- 1-bit output: 180 degree clock output
CLK270 => open, -- 1-bit output: 270 degree clock output
CLK2X => open, -- 1-bit output: 2X clock frequency clock output
CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
CLK90 => open, -- 1-bit output: 90 degree clock output
CLKDV => open, -- 1-bit output: Divided clock output
CLKFX => open, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
-- Control Signals
LOCKED => DCM_locked, -- 1-bit output: DCM_SP Lock Output
PSDONE => open, -- 1-bit output: Phase shift done output
STATUS => DCM_status, -- 8-bit output: DCM_SP status output
CLKFB => DCM_fb_clk, -- 1-bit input: Clock feedback input
CLKIN => PPort_Clk_ibuf, -- 1-bit input: Clock input
DSSEN => '0', -- 1-bit input: Unsupported, specify to GND.
-- Ports for dynamic phase shift
PSCLK => '0', -- 1-bit input: Phase shift clock input
PSEN => '0', -- 1-bit input: Phase shift enable
PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input
RST => DCM_rst -- 1-bit input: Active high reset input
);

 

This didn't change anything either. 

 

Am I missing something? Thanks for your help!

0 Kudos
Teacher muzaffer
Teacher
7,533 Views
Registered: ‎03-31-2012

Re: Setup Timing Error in Spartan 6 design using ISE 14.6

Jump to solution
Airturk,
I think because of the SRLC16 the IOB constraint would not take effect. Can you verify the location of it? If possible use a single flop for the first stage of the register and see if you can place in the IO. With the flop in the IO, the 6+ ns delay should disappear. Separate the first register and make it a FDx by itself and see if you can make it IOB.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Explorer
Explorer
7,530 Views
Registered: ‎09-12-2011

Re: Setup Timing Error in Spartan 6 design using ISE 14.6

Jump to solution

Here is my code where I register the incoming data in respect to its clock two times before using:

 

    Register_Incoming_Data_1: process(clk_cond_in)
    begin
        if rising_edge(clk_cond_in) then
            PP_Data_In_Reg_1              <= PPort_Data_in;
            PP_Data_Valid_In_Reg_1        <= PPort_Data_Valid_in;
            PP_Frame_Valid_In_Reg_Prev_1  <= PP_Frame_Valid_In_Reg_1;            
            PP_Frame_Valid_In_Reg_1       <= PPort_Frame_Valid_in;
        end if;
    end process Register_Incoming_Data_1;

    Register_Incoming_Data_2: process(clk_cond_in)
    begin
        if rising_edge(clk_cond_in) then
            PP_Data_In_Reg_2         <= PP_Data_In_Reg_1;
            PP_Data_Valid_In_Reg_2   <= PP_Data_Valid_In_Reg_1;
        end if;
    end process Register_Incoming_Data_2;

 clk_cond_in is the clock coming from the input pins -> ibufg ->dcm -> bufg

 

PPort_Data_in is the 16 bit data coming from the input pins as well.

 

I think the tools instantiate a SRL to delay the PPort_Data_in one clock cycle and outputs PP_Data_In_Reg_2 implementing this as a shift register.

 

I think changing the location of the pins is the most straightforward solution. I can move them as long as I stay within a subset of pins in Bank 2. 

 

Though I don't seem to be able to find a suitable location, I keep getting the following error:

ERROR:Place:1073 - Placer was unable to create RPM[BUFIO_BUFIOFB_RPMs] for the
   component SP6_BUFIO_INSERT_ML_BUFIO2_5 of type BUFIO for the following
   reason.
   The reason for this issue:
   Some of the logic associated with this structure is locked. This should cause
   the rest of the logic to be locked.  A problem was found where we should
   place BUFIO SP6_BUFIO_INSERT_ML_BUFIO2_5 off the edge of the chip in order to
   satisfy the relative placement requirement of this logic. The following
   components are part of this structure:
      BUFIO   SP6_BUFIO_INSERT_ML_BUFIO2_5
      BUFIOFB   SP6_INS_BUFIO2FB_DCM_ML_BUFIO2FB_9
      NULL Comp
      IOB   PPort_Clk

 

When I let the tools to find a pin for PPort_Clk, it finds and I no longer have timing errors. But the pins that I can select for this are all giving me the error above.

 

Any ideas? Recommendations?

 

Regards, 

 

0 Kudos
Historian
Historian
9,970 Views
Registered: ‎01-23-2009

Re: Setup Timing Error in Spartan 6 design using ISE 14.6

Jump to solution

You need to get the tool NOT to infer the SRL, but instead to use two distinct FFs for each bit. The first one should then be placed in the IOB, and the second one can go elsewhere.

 

One easy way to do this is to add a reset to the flip-flops - SRLs cannot be reset, so if you code a reset, it will force the tool to use flip-flops. There is probably a synthesis directive that you could embed in your code to force it not to use an SRL for that flip-flop (but I don't remember what it is), and you can also turn of SRL inference globally in the synthesis options, but it may just be easier to add the reset...

 

Once you force the tools to give you FFs, and the first FFs gets put in the IOBs, this will meet timing easily.

 

Avrum

0 Kudos
Teacher muzaffer
Teacher
7,519 Views
Registered: ‎03-31-2012

Re: Setup Timing Error in Spartan 6 design using ISE 14.6

Jump to solution
Airturk: what avrum said !
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Explorer
Explorer
7,495 Views
Registered: ‎09-12-2011

Re: Setup Timing Error in Spartan 6 design using ISE 14.6

Jump to solution

Thank you Avrum and Muzaffer. I followed your recommendations and prevented inference of the shift register by using:

 

attribute shreg_extract : string;
attribute shreg_extract of PP_Data_Valid_In_Reg_2: signal is "no";

 

However I now have a longer delay on the clock path, and the reason for that is there is no clock capable pin is available for me to use. I am using a general purpose pin which closest to the dcm as the input. Then the clock goes through ibufg -> dcm -> bufg. 

 

I have posted the timing error below. 

 

What is the way to decrease the clock path delay? Using a clock capable pin would decrease it, but in the version of our board I don't have that option. Can I use phase shift to change it?

 

Maybe another way to achieve this would be to increase the data path delay? I know taking the ffs off of the iobs creates a rather drastic timing delay, therefore I don't think that is an option. Should I add IDELAYs here to control it?

 

Any recommendation is appreciated. Please let me know if I should have considered this question to be answered and opened a new message thread. 

 

Regards, 

 

 

timing_error.png
0 Kudos
Explorer
Explorer
7,476 Views
Registered: ‎09-12-2011

Re: Setup Timing Error in Spartan 6 design using ISE 14.6

Jump to solution

The problem is solved by adding IODELAYs. 

 

Avrum and Muzaffer, thanks for your help. I appreciate it.

0 Kudos