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Anonymous
Not applicable
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Signals coming out of Spartan-3 XC3S1500-4FG320 Differential Output Buffer distorted

Hi,

 

I tried to convert my single ended signal (SClk_P) to Diff Signals using Spartan 3 generic differential output buffer below:

 

OBUFDS_SCLK_P : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => SClk_P_P, -- Diff_p output (connect directly to top-level port)
OB => SClk_P_N, -- Diff_n output (connect directly to top-level port)
I => SClk_P 
);


After implementation, the input SE signal (SClk_P) is correct, but the diff output signal (SClk_P_P or SClk_P_N) is distorted.

 Attach are scope captures of the SE input and Diff output.

The top trace is chip_select active high

The middle trace is clock

The bottom trace is data.

 

On the diff output capture, it seems the clock signal is coupled to the chip_select trace.

 

What could possibly be the cause of this problem? The issue is independent of frequency either in KHz or MHz.

 

Thank you.

 

Buffer_Input_Output_3MHz_capture.JPG
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4 Replies
eteam00
Instructor
Instructor
4,136 Views
Registered: ‎07-21-2009

The scope traces look like logic analyser captures, not analogue waveforms.  Suggest you generate proper scope waveforms which show signal amplitude, edge shape, and trigger voltage relative to the signal being probed.  Then let's see what you've got.

 

Also, please describe the IOSTANDARD being used for the outputs, and the VCCO supply voltage.  And any termination applied to the signals.

 

-- Bob Elkind

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Anonymous
Not applicable
4,122 Views

Here are the signals captured with analog scope and they show the right response.

These signals are mapped to LVDS_25. Does the IOVCC has to be 2.5V, can I supply them with 3.3V IOVCC?

I do not have any termination externally.

Thanks.

Diff_P_output.jpg
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jheslip
Xilinx Employee
Xilinx Employee
4,096 Views
Registered: ‎06-30-2010

Can you describe the scope shot above, you say the middle trace is CLK, this looks correct is there still a problem with it?

If there is try making it single ended again to ensure the single Ended CLK is as you are expecting.

-J
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Anonymous
Not applicable
4,093 Views

No, it's not a problem.

Thanks.

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