Hello
I'm fairly new to FPGA design and I'm trying to communicate a spartan 6 with a cypress EZ-USB (the kit was custom made and I can't modify the cypress firmware). I'm implementing a memory block and the intention is to first read data and write it on memory, and, once all the data is arrived, send it back. The problem is in synthesis it trimms away all the signals with warnings:
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <fdata_41> is unconnected in block <main>.
fdata is inout and once it's trimmed, the rest of the logic is basically useless. I don't know if it's a design issue (and I'm making a begginer's mistake) or if the memory is not properly implemented and that's why the signals are trimmed.
The code and the .syr are attached.
Any help will be grately appreciated.
Thanks in advance.
