05-01-2012 01:31 PM
I'm encountering a synthesis problem with a 19 bit comparator not being synthesized correctly in the Spartan 3A-3400 DSP. I want a 1 bit signal to pulse when a 19 bit counter is equal to 19'd 24576. However in hardware the pulse is firing when the counter is equal to 19'd 57344 instead. This does not occur in behavioral simulation in Isim. Only on the actual hardware. In binary, 24576 is 0000110000000000000 and 57344 is 0001110000000000000.
I've tried writing the code a few different ways.
assign pulse = (counter == 19'd24576);
or a synchronous approach
reg pulse = 1'b0;
always @(posedge clk)
if (counter == 19'd24576)
pulse <= 1'b1;
pulse <= 1'b0;
Interestingly enough if I create a state machine and use 'less than' compare instead of equal compare (a state that waits while the counter < 24576, and then fires the pulse), it works fine. But this approach is not so practical because I need pulses at several multiples of 24576. I strongly prefer to figure out why the equal compare is behaving like this.
Any ideas appreciated. Thanks.
05-02-2012 02:14 AM
05-02-2012 06:24 AM
The version of ISE is 12.1. My clock is about 120 MHz. The timing report is fine, there are no timing failures reported. The false comparison is also not random -its at the number I mentioned, 57344 instead of 24576. Both the synchronous and asynchronous.
05-02-2012 08:23 AM
> However in hardware the pulse is firing when the counter is equal to 19'd 57344 instead.
> This does not occur in behavioral simulation in Isim.
What about a back-annotated simulation with the place and route timing information?
Is there only one clock used for both the counter that is being compared and where the "pulse" is used?
05-03-2012 05:44 AM
05-03-2012 07:13 AM
Good catch! I bet you that is it: he has a 16 bit integer, so it has a sign bit, and the constant is too big to fit.
Like Peter used to say, "first look for the obvious."