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g3tech
Visitor
Visitor
5,859 Views
Registered: ‎09-29-2011

Spartan 3A DSP 3400 Comparator synthesized incorrectly

I'm encountering a synthesis problem with a 19 bit comparator not being synthesized correctly in the Spartan 3A-3400 DSP. I want a 1 bit signal to pulse when a 19 bit counter is equal to 19'd 24576. However in hardware the pulse is firing when the counter is equal to 19'd 57344 instead. This does not occur in behavioral simulation in Isim. Only on the actual hardware. In binary, 24576 is 0000110000000000000 and 57344 is 0001110000000000000.

 

I've tried writing the code a few different ways.

 

assign pulse  = (counter == 19'd24576);

 

or a synchronous approach

 

 

reg pulse = 1'b0;

always @(posedge clk)

begin

 

if (counter == 19'd24576)

pulse <= 1'b1;

else

pulse <= 1'b0;

end

 

 

Interestingly enough if I create a state machine and use 'less than' compare instead of equal compare (a state that waits while the counter < 24576, and then fires the pulse), it works fine. But this approach is not  so practical because I need pulses at several multiples of 24576. I strongly prefer to figure out why the equal compare is behaving like this.

 

Any ideas appreciated. Thanks.

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6 Replies
austin
Scholar
Scholar
5,852 Views
Registered: ‎02-27-2008

g,

 

An asynshronous approach will glitch (and fail).


A synchronous approach should work.

Austin Lesea
Principal Engineer
Xilinx San Jose
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rcingham
Teacher
Teacher
5,842 Views
Registered: ‎09-09-2010

What version of ISE?
How fast is the clock?
What report from post-PAR Timing Analysis?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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g3tech
Visitor
Visitor
5,838 Views
Registered: ‎09-29-2011

Thanks.

The version of ISE is 12.1. My clock is about 120 MHz. The timing report is fine, there are no timing failures reported. The false comparison is also not random -its at the number I mentioned, 57344 instead of 24576. Both the synchronous and asynchronous.

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mcgett
Xilinx Employee
Xilinx Employee
5,833 Views
Registered: ‎01-03-2008

> However in hardware the pulse is firing when the counter is equal to 19'd 57344 instead.

> This does not occur in behavioral simulation in Isim.

 

What about a back-annotated simulation with the place and route timing information?

 

Is there only one clock used for both the counter that is being compared and where the "pulse" is used?

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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rcingham
Teacher
Teacher
5,824 Views
Registered: ‎09-09-2010

24576 = 0x6000
57344 = 0xE000
57344-24576 = 32768 = 2^15
Is there an implied truncation somewhere in the RTL code?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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austin
Scholar
Scholar
5,820 Views
Registered: ‎02-27-2008

r,

 

Good catch!  I bet you that is it:  he has a 16 bit integer, so it has a sign bit, and the constant is too big to fit.

 

Like Peter used to say, "first look for the obvious."

Austin Lesea
Principal Engineer
Xilinx San Jose
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