07-06-2013 03:47 PM
Hi For couple of days i've been trying to implement the spi interface i have simulated it which shows that it works and ive checked with the scope aswell. All the proper commands are sent the correct polarity etc. but the dac still doesnt output anything. I'm triying to send CMD = 0x3 ADDR = 0x0 DATA = 0xFF0. I've inversed it in my code so that it fits the msb first rule
SCK is generated ok it's at 4.127MHZ. CS line is pulled low when the data transmisson starts. Then pulled back high. To sum it all up evrything with the spi bus works perfectly but the DAC(LTC2624) doesnt work. Nothing is outputed
Here is the code:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DAC is port ( CLK : in STD_LOGIC; SCK : out STD_LOGIC := '0'; MOSI : out STD_LOGIC := '0'; CSDAC : out STD_LOGIC := '1'; SPI_SS_B : out STD_LOGIC; AMP_CS : out STD_LOGIC; AD_CONV : out STD_LOGIC; SF_CE0 : out STD_LOGIC; FPGA_INIT_B : out STD_LOGIC; DEBUG : out STD_LOGIC := '1' ); end DAC; architecture Behavioral of DAC is Signal Counter : Integer range 0 to 6 := 0; Signal Counter2 : Integer range 0 to 33 := 0; Signal CurrentBit : Integer range 0 to 33 := 0; Signal Fixed : STD_LOGIC := '0'; Signal DataSent : STD_LOGIC := '0'; Constant Data : STD_LOGIC_VECTOR(31 downto 0) := X"0FFF0C00"; Signal Slope_last : STD_LOGIC := '0'; Signal Slope : STD_LOGIC := '0'; begin WriteDac : process(CLK) begin if rising_edge(CLK) then if Counter = 5 then Counter <= 0; Slope_last <= Slope; Slope <= not(Slope); if Slope_last = '0' and Slope = '1' then if Fixed = '1' then if DataSent = '0' then if CurrentBit <= 31 then CSDAC <= '0'; DEBUG <= '0'; MOSI <= Data(CurrentBit); CurrentBit <= CurrentBit +1; else MOSI <= '0'; CSDAC <= '1'; DEBUG <= '1'; DataSent <= '1'; end if; end if; else if Counter2 <= 31 then CSDAC <= '1'; DEBUG <= '1'; Counter2 <= Counter2 + 1; else Fixed <= '1'; MOSI <= '0'; end if; end if; end if; else Counter <= Counter + 1; end if; end if; end process; SCK <= SLOPE; SPI_SS_B <= '1'; AMP_CS <= '1'; AD_CONV <= '0'; SF_CE0 <= '1'; FPGA_INIT_B <= '0'; end Behavioral;
07-08-2013 03:23 PM
Did you simulate the design?
Why are you using a counter to index the bits in the outgoing data register instead of just loading a shift register?