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Observer sandeep424
Observer
6,317 Views
Registered: ‎12-17-2009

Spartan 3E

Does Spartan 3E  come with a build-in Microblaze processor or its an option which we can order, then only it is embedded in the Kit. I know that spartan 6 has a built in processor. So, is the Spartan 3E is same as Spartan 6 that it has a built in processor.

 

Could anyone help me with this doubt?

 

Thanking you in advance.

 

-Sandeep

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5 Replies
Xilinx Employee
Xilinx Employee
6,310 Views
Registered: ‎08-13-2007

Re: Spartan 3E

Neither Spartan-3E or Spartan-6 have "built in processors". The MicroBlaze is a "soft processor" which means it is built out of general purpose FPGA resources like LUTs (and shift registers, distributed memory), FFs, BRAMs, etc. It is customizable based on the features you need. You can also use multiple of them if you have the resources in your target device.


This is different than a "hard processor" where the processor is physically immersed on the FPGA die in a specific location and configuration during IC design & layout. The only current Xilinx FPGAs with hard or immersed processors are:

Virtex-II Pro: 1 or 2 PPC405s

Virtex-4FX: 1 or 2 PPC405s

Virtex-5 FXT: 1 or 2 PPC440s

Hard processors are not customizable the same way - you either use them or you don't. Though their peripheral sets are generally built out of fabric resources.

 

BTW, you don't have to order MicroBlaze with the FPGA. You do have to purchase the development kit: EDK which includes the tools, processor, and some of the associated IP. Then you can deploy MicroBlaze on as many Xilinx FPGAs as you can with no run-time royalties, ordering considerations, etc.

 

There are other soft processors as well: PicoBlaze/kcpsm3, LEON, Cortex M3, OpenRISC, etc.

 

bt

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Observer sandeep424
Observer
6,281 Views
Registered: ‎12-17-2009

Re: Spartan 3E

Thank You very much timpe..this has been a great help to me in deciding to think also about spartan -6.

 

and one small doubt...I was thinking to have a block RAM size of 128x256(width=128,depth=256). So,will Spartan 6 satisfy these requirements. It was told to me that for coding purpose that we use Core generator of ISE to generate arbitary RAM to use for us in the code purpose,is this also right.

 

Thank you in advance.

 

-Sandeep

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Historian
Historian
6,273 Views
Registered: ‎02-25-2008

Re: Spartan 3E


sandeep424 wrote: 

and one small doubt...I was thinking to have a block RAM size of 128x256(width=128,depth=256). So,will Spartan 6 satisfy these requirements. It was told to me that for coding purpose that we use Core generator of ISE to generate arbitary RAM to use for us in the code purpose,is this also right.

 


-Sandeep


RTFDS. That nice document tells you everything you need to know about the device block RAMs.

 

As for using Core Generator, just don't. It's simple enough to write HDL that will properly infer your memory. Read the fine Synthesis and Simulation guide. It's all there.

----------------------------Yes, I do this for a living.
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Xilinx Employee
Xilinx Employee
6,270 Views
Registered: ‎08-13-2007

Re: Spartan 3E

Core Generator is one way to use BlockRAM. You can also use:

-HDL inference  (see XST user guide)

-unimacros (see S6 Library guide)

-instantiation (see S6 Library guide)

There are tradeoffs here in portability, software support, maintenance, etc.

 

I'm not personally a big fan of CoreGen for memory. HDL inference is the most portable but doesn't support some of the advanced features, whch is usually when I move to direct instantiation in a wrapper module.

 

Spartan-6 follows the Virtex documentation convention rather than the traditional Spartan approach of packing everything in the datasheet. So you'll see specs in the datasheet and specific functional descriptions in the user guides, e.g.:

http://www.xilinx.com/support/documentation/user_guides/ug383.pdf (Spartan-6 FPGA Block RAM Resources User Guide)

 

And there's some legacy documentation which can also be helpful:

http://www.xilinx.com/support/documentation/white_papers/wp335.pdf (Creative Uses of Block RAM)
http://www.xilinx.com/support/documentation/application_notes/xapp463.pdf (Using Block RAM in Spartan-3 Generation FPGAs)

 

And some things that might not initially be obvious:

http://forums.xilinx.com/t5/PLD-Blog/Reducing-BRAM-Power-Consumption/ba-p/11328 (Reducing BRAM Power Consumption)
http://www.xilinx.com/support/answers/21870.htm (Virtex-II/-II Pro/-4 block RAM - Do the setup/hold times for the Address inputs need to be met, even if the output is unused and WE is deasserted?)

 

Spartan-6 BRAM has separate byte enables as introduced on Spartan-3A and Virtex-4. It is also able to fractured into 2 separate 2 9Kb BRAMs.

But see the existing documentation for the full scoop.

 

bt

 

Message Edited by timpe on 12-18-2009 08:10 PM
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Highlighted
4,895 Views
Registered: ‎11-08-2012

Re: Spartan 3E

I am working with the FPGA Spartan 3E   and need to implement the exponential function (Euler number e ^ x) and the values of "x" are floating  numbers.

Because Xilinx has no direct exponential function,What tool Can I use to implement this function,

 I found some information that says that you can connect the spartan 3e board with LabVIEW, or with Mathlab,  or with microblaze,

What is the best option to implement the exponential function

Does Microblable have the exponencial function (e^x) ???

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