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Explorer
Explorer
11,932 Views
Registered: ‎11-23-2009

Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

Hallo,

 

we plan a design with a Spartan-6 LX150T with 2 FMC interfaces. Thus mostly LVDS I/O. The clocks are also mostly LVDS.

 

When looking through UG382, especially Figure 1-3 and 1-4, I deduce that only 4 of the 8 BUFGMUX associated with each device half can be reached when differential clocks are used. Simply because only the master GCLK counts (the odd numbered one), and the way GCLKs are routed to the BUFGMUXs. Bottom line seems to be:

 

  If differential clocks are used, only 8 of the 16 BUFGMUX can be reached

 

It that really true ? Or am I overlooking something here ?

 

Any help or hint very welcome.

15 Replies
Highlighted
Teacher eteam00
Teacher
11,928 Views
Registered: ‎07-21-2009

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

Why not cobble up a trial design, place, and route, and understand with certainty what your pinout options might be?  This shouldn't take more than an hour or two.

 

And don't forget:  In the Spartan-6 family, LVDS output is available only on IO banks 0 and 2

 

-- Bob Elkind

SIGNATURE:
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Summary:
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Explorer
Explorer
11,924 Views
Registered: ‎11-23-2009

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

Hi Bob,

 

thanks for the answer.

 

on trial design:

sure we did that. But it's very hard to understand why the routing was choosen the way it is. Combining always odd with odd and even with even numbered GCLKs on the BUFGMUX input lines does maximal damage when differential inputs are used, combining odd with even GCLKs would have avoided. That's why we still wonder whether there is a way around this limitation.

 

on bank 0+2:

found that, in ug381 (SelectIO UG). I couldn't find any hint on this very essential restriction in the pinout tables in ug385, where this should be clearly stated in a prominent place. The wording in Table 1-6 for IO_LXXY is certainly misleading.

Teacher eteam00
Teacher
11,923 Views
Registered: ‎07-21-2009

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

Your problem isn't entirely clear to me...  Perhaps you might post your code for clock input, generation, distribution, and usage -- with some minimal description to guide us through the code.  This would help in understanding what you are trying to accomplish.

 

on bank 0+2:

found that, in ug381 (SelectIO UG). I couldn't find any hint on this very essential restriction in the pinout tables in ug385, where this should be clearly stated in a prominent place. The wording in Table 1-6 for IO_LXXY is certainly misleading.

UG381 (v1.4, the latest version as this is being written) Table 1-6 seems very clear on the Bank 0+2 restriction.  I don't see any references to IO_LXXY, misleading or otherwise.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Xilinx Employee
Xilinx Employee
11,913 Views
Registered: ‎02-09-2011

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

In spartan-6, total 32 GCLKs single ended (can be used as 16 differential clock inputs), 16 BUFGMUXs are there (8 in top and 8 in bottom). Number of GCLKs in each bank is 8 single ended (can be used as 4 differential)

Total 8 differential GCLKs in Bank 0 and 1 can access 8 top BUFGMUXs.

Total 8 differential GCLKs in Bank 2 and 3 can access 8 bottom BUFGMUXs.

 

Hope this clarifies your query.

Explorer
Explorer
11,898 Views
Registered: ‎11-23-2009

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

Hi Bob,

 

you are right, Table 1-6 in ug381 (SelectIO UG) is ok and unambiguous.

 

My remark was on Table 1-6 in ug385 (Pinouts). At least in V2.0 the row on IO_LXXY_# is imho misleading, it states 'Description' that all user I/O pins are capable of differential signaling and in 'Direction' Input/Output. This suggests that all user I/O pins can do differential input and output, which we know isn't true.

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Explorer
Explorer
11,897 Views
Registered: ‎11-23-2009

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

Hi Krishna,

 

yes, there are 32 GCLK pins, which can be used as 16 differential inputs. There are also 16 BUFGMUX. But apparently there are not routing resources which allow to directly connect more than 8 differential clocks to BUFGs. A simple test design works nice for 8 differential clocks, when 9 differential clocks are used (via IBUFGDS connected to a BUFG) I get a MAP error

 

  ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found that

    are not placed at an optimal clock IOB / BUFGMUX site pair.

    ...

    There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they

    are not being used.

 

Using 16 single ended clocks works fine, all 16 BUFGs are used.

 

Figures 1-3 and 1-4 in ug382 (Clocking UG) show the routing possibilities, and these figues show that the odd numbered GCLKs, which are the _P or master sides of the differential pair, are combined such that only four BUFGMUX can be used for each device half, or 8 in total.

 

This is consistent with what a quick check with ISE shows.

 

So I still wonder whether there is a way around this limitation.

Any hint very appreciated.

 

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Teacher eteam00
Teacher
11,895 Views
Registered: ‎07-21-2009

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

...it states 'Description' that all user I/O pins are capable of differential signaling and in 'Direction' Input/Output.

 

yes, can do differential and can do output, but not both at the same time (as you've discovered)  :)

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Xilinx Employee
Xilinx Employee
11,871 Views
Registered: ‎02-09-2011

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

Hello,

 

You can achieve it using BUFIO2s.

For example take assumption as below.

As per Figure 1-3,

- GCLK18&19 pair drives BUFGMUX_X2Y2

- GCLK16&17 pair drives BUFGMUX_X3Y5

- GCLK14&15 pair drives BUFGMUX_X3Y6

- GCLK12&13 pair drives BUFGMUX_X3Y8

 

As per your observation other GCLK pairs can not drive BUGMUXes as _p pins connects to BUFGMUXes which are already connected GCLK pairs mentioned above.

 

So its a conflict, two pins can not directly drive same BUFGMUX so router is not able to route.

 

The work around to drive atlease other 2 BUFGMUXes using other 2 GCLK pairs is to use BUFIO2s attached to _p pins DIVCLK of that BUFIO2 drives BUFGMUX.

 

- GCLK11&10 pair drives BUFIO2_X4Y21 and DIVCLK of this BUFIO2_X4Y21 drives BUFGMUX_X2Y1

- GCLK8&9 pair drives BUFIO2_X3Y11 and DIVCLK of this BUFIO2_X3Y11 drives BUFGMUX_X3Y7

 

But BUFGMUX_X2Y3 and BUFGMUX_X2Y4 can not be driven in any way using other GCLK pins.

The reason for this is both the inputs of these BUFGMUXes connected to _n pins.

 

Final note is, in total FPGA,  

8 BUFGMUXes can be driven using differential GCLK pins if you are not using BUFIO2s.

12 BUFGMUXes can be driven using differential GCLK pins if you are using BUFIO2s also.

 

Hope this helps...

 

 

Scholar samcossais
Scholar
11,332 Views
Registered: ‎12-07-2009

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

I have the same problem as wfjmueller.

And in my opinion, what he believes is true (if we use differential inputs, we will be able to reach only 8 BUFGs of the 16) and what krishna says is wrong.

 

Because Krishna say that according to Figure 1-3 of the clock user guide :

- GCLK16&17 pair drives BUFGMUX_X3Y5

- GCLK14&15 pair drives BUFGMUX_X3Y6


This is wrong no ? Actually no differential pair (=odd GCLK numbers) can reach these two BUFGMUX (according to this same figure 1-3. Check it again please.

 

And connecting to BUFG via BUFIO2 won't change anything to this fact. Am I wrong ?

 

Here are my explanations :

In the case of GCLK 17&16 for instance, if our clock input is differential, GCLK16 is the differential slave (n pin) and I believe we can't use its connections to internal ressources in this case. Now looking at  GCLK17, we can see it can connect directly to BUFG_X2Y3 or BUFG_X2Y4, or connect through BUFIO2_X2Y26 to these same 2 BUFGs, or connect through BUFIO2_X4Y26 to BUFG_X3Y7 or BUFG_X3Y8.

However, BUFG_X3Y7 and BUFG_X3Y8 can already be reached by an odd number GCLK (GCLK13) which we will be able to use in differential mode anyway because odd numbers are ok. The problem is with even numbers and there is no way to avoid it by using BUFIO2 paths because these paths connects odd GCLK together and even GCLK together (which seems in my opinion quite awkward to be honest).

 

So I'm just thinking this is a kind of flaw in the Spartan-6 design. It is not efficient for people using differential inputs because only half of the BUFGs can be reached directly by clock inputs.

 

Am I wrong somewhere ?

Tags (1)
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Scholar samcossais
Scholar
6,024 Views
Registered: ‎12-07-2009

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

I guess I know who put the "Zombie thread" tag to my post and I just want to tell him that, whatever he thinks about this thread being old or anything (which is not exactly the case cos 2011/10 is not that old), the answers given didn't solve the problem (they were not even marked as "solution") so asking again is not too late for persons like me who encounter the same issue.

 

So please keep your stupid tags for you and give us some intelligent answer.

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Teacher eteam00
Teacher
6,014 Views
Registered: ‎07-21-2009

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

So I'm just thinking this is a kind of flaw in the Spartan-6 design.

 

Flaw?  Don't think so.  It's a design optimisation.

 

Remember:  Spartan is the budget FPGA series. It provides the most marketable combination of functions for most applications and designers.  It is not Spartan's 'mission' to be all things to all people -- that costs more money, more die area, more production test time, more software development time, etc. etc.  The cost-efficient compromises, chosen wisely, are what make Spartan devices so popular.

 

In other words, the limitation you describe is a choice, not a flaw.

 

It is not efficient for people using differential inputs because only half of the BUFGs can be reached directly by clock inputs.

 

For most applications, this limitation is acceptable.  For some applications, it is either an inconvenience or a show-stopper.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Historian
Historian
6,011 Views
Registered: ‎02-25-2008

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?


@samcossais wrote:

So I'm just thinking this is a kind of flaw in the Spartan-6 design. It is not efficient for people using differential inputs because only half of the BUFGs can be reached directly by clock inputs.


You're not wrong, and the same idiocy exists in the Spartan 3A/3E devices, too. I don't even know how to use the Left-Hand and Right-Hand clocks without the tools throwing an obtuse warning about "Competing Global/Side clock buffers."

----------------------------Yes, I do this for a living.
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Scholar samcossais
Scholar
6,008 Views
Registered: ‎12-07-2009

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

eteam00 >

I quite disagree with you. Something optimized compared to another mean it does things better with a identical cost, or it does it as well but cheaper.

 

However here we just have an example of something not optimized. It costs the same and does things less well than if some of the GCLKs and some of the BUFIO2/BUFG had been swapped. Indeed I don't think that swapping lines would change anything in cost (or perf), because it's swapping, not adding new lines nor adding muxes.

 

That's why I say it appears that Xilinx tried to do something complicated by putting a lot of possibilities for GCLK to BUFIO/BUGs direct access, but it's just not efficient at all.

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Scholar samcossais
Scholar
6,007 Views
Registered: ‎12-07-2009

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?

Thanks for the answer bassman.

 

In a previous project I used a Spartan3A-DSP to do almost the same thing I do now (but the design was smaller). I also had some clocking problems but at that time I didn't use the direct connexion from GCLK to BUFG so I didn't figure out something was not optimized there. Maybe it was I don't know.

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Historian
Historian
6,000 Views
Registered: ‎02-25-2008

Re: Spartan-6: GCLK and BUFGMUX connectivity when differential clocks are used: only 8 of 16 BUFGs accessible ?


@samcossais wrote:

Thanks for the answer bassman.

 

In a previous project I used a Spartan3A-DSP to do almost the same thing I do now (but the design was smaller). I also had some clocking problems but at that time I didn't use the direct connexion from GCLK to BUFG so I didn't figure out something was not optimized there. Maybe it was I don't know.


Sam, in another thread, I complain about the S3A's inability to use the LH and RH clocks. I wanted to use them because the tools were complaining about inefficient routing (not using the direct path from pin to global buffer) when I tried to use three LVDS-input global clocks on one side of the FPGA. So I added the CLOCK_DEDICATED_ROUTE = FALSE; constraint to the clock pin that failed. The tools then were able to put the clock signal from the pin directly to the global buffer as one would expect. In other words, by telling it to not use the dedicated route, it used the dedicated route.

 

Seriously, I wasted an afternoon trying to get this to work without resorting to what Xilinx claims is a last-resort.

 

I still can't get the LH and RH clocks to work. 

----------------------------Yes, I do this for a living.
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