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Visitor
Visitor
5,493 Views
Registered: ‎06-10-2016

Spartan 6 LX100T - Everytime i generate image, i see surprise in the functionality. Everytime i get new results.

Hi,

 

I am using Spartan 6 LX100T device. I have pcie, other glue logic inside the fpga, pcie runs at 62.5Mhz, other glue logic uses 2 Mhz and 49Mhz. The problem i see, everytime i generate bit file and load into board. I see new results, mean the functionality working in previous image is not working in current image, even though their is no change in rtl. When i tryied to diff the srr report, i see some changes.

Need suggestion to fix this issue.

 

Thanks

jayaprakashreddy y 

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Professor
Professor
5,462 Views
Registered: ‎08-14-2007

This sounds like a clock domain crossing (CDC) issue.  You need to go through the paths with clock domain crossings and make sure they are handled correctly.  ISE only checks for proper setup and hold timing on CDC paths between related clocks, ie clocks that come from the same input pin through DCM or PLL components.  If your clocks (2M, 49M, 62.5M) are not derived from the same clock source, there will be asynchronous clock crossings between the domains which are not checked by ISE.  These need to be handled correctly by design.

-- Gabor
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