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Newbie cherwa
Newbie
3,035 Views
Registered: ‎04-27-2017

Spartan 6 Pll_Base phase aligned clocks divider not multiple of multiplier

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Hey,

 

I'm tying to generate a phased aligned 100MHz and 50MHz clk from a 40MHz clk.

 

pll_base_inst: pll_base
generic map (
BANDWIDTH => "optimized",
CLKFBOUT_MULT => 20, --800MHz internal
CLKFBOUT_PHASE => 0.0,
CLKIN_PERIOD => 25.0, --40MHz input
CLKOUT0_DIVIDE => 4, --200MHz clock
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT0_PHASE => 0.0,
CLKOUT1_DIVIDE => 8, --100MHz clock
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0,
CLKOUT2_DIVIDE => 16, --50MHz clock
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT2_PHASE => 0.0,
CLK_FEEDBACK => "clkfbout",
COMPENSATION => "system_synchronous",
DIVCLK_DIVIDE => 1,
REF_JITTER => 0.100,
RESET_ON_LOSS_OF_LOCK => false)
port map (
CLKFBOUT => PllClockFeedbackOut,
CLKOUT0 => open,
CLKOUT1 => PllClock100MHz,
CLKOUT2 => PllClock50MHz,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => aPllLocked,
CLKFBIN => PllClockFeedbackIn,
CLKIN => Clk40MHz,
RST => aPllReset);

 

--Pll feedback.
PllClockFeedbackBuffer: bufg
port map (
I => PllClockFeedbackOut,
O => PllClockFeedbackIn);

 

My question is, will both the PllClock100MHz and PllClock50MHz be phase aligned if the CLKOUT*_DIVIDE isn't a multiple of CLKFBOUT_MULT?

 

Thanks,

Cherwa

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1 Solution

Accepted Solutions
Historian
Historian
5,588 Views
Registered: ‎01-23-2009

Re: Spartan 6 Pll_Base phase aligned clocks divider not multiple of multiplier

Jump to solution

Since we are using different divisors, is it guaranteed that both output clks will start at the same time so that the outputs always have deterministic phase?

 

Yes.

 

"Start at the same time" is a hard thing to state. However, since they are divided outputs running on the same VCO clock, they will align once every Least Common Multiple of the periods of the two clocks. Since your two clocks differ by a factor of 2, that means every 2nd clock will align.

 

The nominal phase between them when they align will be 0, with some (small) uncertainty - it is characterized as Tstaphaoffset in the Datasheet (DS162), which has a maximum of 120ps for all speedgrades except 1L, which is 150ps.

The tools understand this static phase offset, and take it into account on paths that cross between the two synchronous domains (and the tools also understand the 2:1 clock ratio between them).

 

Put simply simply, the tools understand the timing relationships between the two clocks. On any path between them, if the tool says the path meets timing, then it will be OK. For clocks with these kinds of relationships (100MHz and 50Mhz), if you use the same buffers (i.e. both BUFGs) then it is perfectly safe to cross synchronously between these domains (we do it all the time).

 

Avrum

3 Replies
Historian
Historian
3,030 Views
Registered: ‎01-23-2009

Re: Spartan 6 Pll_Base phase aligned clocks divider not multiple of multiplier

Jump to solution

The outputs of the PLL are always aligned.

 

The CLKFBOUT_MULT (along with DIVCLK_DIVIDE) determine the frequency of the voltage controlled oscillator (VCO) - this is the primary frequency of the PLL. All the outputs CLKOUT0-CLKOUTn are simple divisions of the VCO frequency (in the MMCM some of these dividers can be in increments of 1/8, but in the PLL in the Spartan-6 they are pure integers). So, pretty much by definition, the different outputs are in phase - they are synchronous to the VCO frequency.

 

If course you can modify the alignment using the CLKOUTx_PHASE attributes, which are controllable in increments of the VCO period divided by 8.

 

Avrum

Newbie cherwa
Newbie
2,969 Views
Registered: ‎04-27-2017

Re: Spartan 6 Pll_Base phase aligned clocks divider not multiple of multiplier

Jump to solution

Hey Avrum,

 

Since we are using different divisors, is it guaranteed that both output clks will start at the same time so that the outputs always have deterministic phase?

 

Thanks,

Cherwa 

0 Kudos
Historian
Historian
5,589 Views
Registered: ‎01-23-2009

Re: Spartan 6 Pll_Base phase aligned clocks divider not multiple of multiplier

Jump to solution

Since we are using different divisors, is it guaranteed that both output clks will start at the same time so that the outputs always have deterministic phase?

 

Yes.

 

"Start at the same time" is a hard thing to state. However, since they are divided outputs running on the same VCO clock, they will align once every Least Common Multiple of the periods of the two clocks. Since your two clocks differ by a factor of 2, that means every 2nd clock will align.

 

The nominal phase between them when they align will be 0, with some (small) uncertainty - it is characterized as Tstaphaoffset in the Datasheet (DS162), which has a maximum of 120ps for all speedgrades except 1L, which is 150ps.

The tools understand this static phase offset, and take it into account on paths that cross between the two synchronous domains (and the tools also understand the 2:1 clock ratio between them).

 

Put simply simply, the tools understand the timing relationships between the two clocks. On any path between them, if the tool says the path meets timing, then it will be OK. For clocks with these kinds of relationships (100MHz and 50Mhz), if you use the same buffers (i.e. both BUFGs) then it is perfectly safe to cross synchronously between these domains (we do it all the time).

 

Avrum