cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
sebastianro
Participant
Participant
10,512 Views
Registered: ‎10-22-2010

Spartan 6 configuration problem

Jump to solution

Hi,

 

I'm trying to configure a Spartan 6 on custom board through JTAG and doens't seem to work, so some questions:

 

1. Do the values on  PROGRAM_B and INIT_B count on JTAG programming? I mean they are Pulled-Up/ Low as required but I don't have other drivers on them

2. Can this be a CRC error?

3. The Init_b led on my board goes  high, low, high on power-up and remain permemanenty high. Is this a problem?

 

Thanks

0 Kudos
1 Solution

Accepted Solutions
gszakacs
Professor
Professor
13,446 Views
Registered: ‎08-14-2007

Some points:

 

Mode pins are sampled when INIT_B is released by the internal logic.  If INIT_B has

already gone high before you drive it low, then you will not hold off the start of configuration.

 

PROGRAM_B is like a global reset.  Pulling it low will cause the FPGA to "forget" it's configuration

and return to it's initial power-on state.  You can re-assert PROGRAM_B (low) at any time to

restart configuration, and you can hold it low to delay configuration if necessary.  Using PROGRAM_B

to start configuration and holding INIT_B low from the assertion of PROGRAM_B until you are

ready to configure the part is safer than just using INIT_B.

 

INIT_B becomes a status output after the actual configuration process starts to download the

bitstream.  If INIT_B re-asserts low after the bitstream has started loading, it means you

got a CRC error.  There are a number of reasons you might get a CRC error, especially when

using your own software.  One common problem is using the wrong bit transmission order

when serializing the data.  Another common problem that can result in CRC error is poor

signal integrity on the CCLK or JTAG TCK pin.

 

Search through the forums for common configuration problems and you'll see that

you're not alone in having issues on a new design.  These problems can be hard enough

to debug when you use the known-good Impact software, and only get harder when you

add your own software as another unknown.

 

-- Gabor

-- Gabor

View solution in original post

10 Replies
eteam00
Instructor
Instructor
10,511 Views
Registered: ‎07-21-2009

1. Do the values on  PROGRAM_B and INIT_B count on JTAG programming? I mean they are Pulled-Up/ Low as required but I don't have other drivers on them

PROG_B must be held HIGH to configure FPGA via JTAG.  I think (not sure) holding INIT_B LOW would be a bad idea.

2. Can this be a CRC error?

Who knows what "this" is?  If you are using Impact, what does Impact report?

3. The Init_b led on my board goes  high, low, high on power-up and remain permemanenty high. Is this a problem?

This is expected and normal behaviour.  On power-up or on pulse of PROG_B, INIT_B will pulse LOW while resetting internal FPGA state, and then INIT_B will float HIGH (it's open-drain) to signal that Mx: pins have been sampled and FPGA is ready to be configured.  If INIT_B goes LOW again before configuration is done, this would signal a configuration error such as CRC error.

 

Do you have multiple copies of your board?  Do they all behave the same?  Is Product ID fetched correctly?  Have you checked power supplies?

 

You may need to use an oscilloscope, to check JTAG signals.

What debugging have you done so far?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
sebastianro
Participant
Participant
10,503 Views
Registered: ‎10-22-2010

Thanks,

 

2. I'm not using impact, unfourtunately.

 

3. I missinterpreted that, I have an LED on INIT_B which lights, just like in Xilinx' example schematics, if INIT_B is low, so I have: low, high, low on this pin (INIT_B is active low, according to Xilinx spec). So for me, INIT_B is low most part of my design, even when I try to program the FPGA, so I think this means it delays the configuration until it quits it: "

Before the Mode pins are sampled, INIT_B is an input that can be held Low to delay configuration. Before the Mode pins are sampled, INIT_B is aninput that can be held Low to delay configuration.". Or do I get past the mode pins sampling with those low, high, low transitions and the returning to low is normal because I'm using JTAG configuration.
4. I don't have multiple boards. Product ID is fetched corectly and the voltages are within recomended values.
Thanks again

 

0 Kudos
mcgett
Xilinx Employee
Xilinx Employee
10,498 Views
Registered: ‎01-03-2008
PROGRAM_B and INIT_B must both be high (same level as VCCO of the bank that are in) for the device to configure.

If you are not using impact then what are you using?
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
eteam00
Instructor
Instructor
10,496 Views
Registered: ‎07-21-2009

2. I'm not using impact, unfourtunately.

Why don't you rig up a connector for a Platform Cable, and give Impact a try.  This will get you more helpful support, and help you with debugging.

Or do I get past the mode pins sampling with those low, high, low transitions and the returning to low is normal because I'm using JTAG configuration.

JTAG will over-ride mode pins settings.

I don't have multiple boards.

If you get desperate, you may want to build second board (with at least the power supplies and the FPGA on the board).  No hurry on this.

Product ID is fetched corectly

Good sign that the JTAG interface is working correctly.   If the Product ID fetch is reliable (always works), this would suggest you have a config data problem (wrong data, or wrong formatting of data).

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
sebastianro
Participant
Participant
10,489 Views
Registered: ‎10-22-2010
Do i have to make some specific setings to the generate programming file process, I used default setings.
0 Kudos
sebastianro
Participant
Participant
10,489 Views
Registered: ‎10-22-2010
Do i have to make some specific setings to the generate programming file process, I used default settings.
0 Kudos
eteam00
Instructor
Instructor
10,487 Views
Registered: ‎07-21-2009

Your hardware is not yet verified.

Your JTAG software and process flow is unknown, and not yet verified.

 

The IMPACT flow is well supported and documented.  If you are successful programming your FPGA via IMPACT, this will verify the hardware and allow you to focus your efforts -- with certainty -- on your JTAG software and process flow.  If IMPACT programming effort is unsuccessful, the IMPACT reports will help to identify where you should be focusing your attention.

 

Until you verify either the software and process flow, or the hardware, you are still unsure where to focus your debugging efforts.

 

If you are concerned about your software JTAG programming tool, it would be logical to consult the tool's supplier for support and guidance.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
gszakacs
Professor
Professor
13,447 Views
Registered: ‎08-14-2007

Some points:

 

Mode pins are sampled when INIT_B is released by the internal logic.  If INIT_B has

already gone high before you drive it low, then you will not hold off the start of configuration.

 

PROGRAM_B is like a global reset.  Pulling it low will cause the FPGA to "forget" it's configuration

and return to it's initial power-on state.  You can re-assert PROGRAM_B (low) at any time to

restart configuration, and you can hold it low to delay configuration if necessary.  Using PROGRAM_B

to start configuration and holding INIT_B low from the assertion of PROGRAM_B until you are

ready to configure the part is safer than just using INIT_B.

 

INIT_B becomes a status output after the actual configuration process starts to download the

bitstream.  If INIT_B re-asserts low after the bitstream has started loading, it means you

got a CRC error.  There are a number of reasons you might get a CRC error, especially when

using your own software.  One common problem is using the wrong bit transmission order

when serializing the data.  Another common problem that can result in CRC error is poor

signal integrity on the CCLK or JTAG TCK pin.

 

Search through the forums for common configuration problems and you'll see that

you're not alone in having issues on a new design.  These problems can be hard enough

to debug when you use the known-good Impact software, and only get harder when you

add your own software as another unknown.

 

-- Gabor

-- Gabor

View solution in original post

sebastianro
Participant
Participant
10,465 Views
Registered: ‎10-22-2010
Thanks guys,

finally it worked with the custom cable, (I think it was a CRC error, sometimes it worked, sometimes not). With Xilinx cable, it works fine in the end.
0 Kudos
eteam00
Instructor
Instructor
2,759 Views
Registered: ‎07-21-2009

finally it worked with the custom cable, (I think it was a CRC error, sometimes it worked, sometimes not).

This would suggest a timing error or signal integrity problem.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.