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9,039 Views
Registered: ‎03-15-2013

Spartan 6 issue FD, FD_1 optimized to an IDDR2

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Hi,

I'm implementing Xapp1015 on a spartan6.

Everything works fine, with a pll generating my four 270Mhz clocks with bufgs.

As the designed is used localy, I changed the implentation with 4 bufhs.

That works if I just implement the asi rx to an asi tx.

Now if I try to implement that in my full design I get the follwing issue:

 

# END of Global Clock Net Loads Distribution Report:
######################################################################################


ERROR:Place:1163 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this
design and either lock the clock placement or area locate the logic driven by the clocks so that that the clocks may
be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement for this
architecture is that only 16 of all clocks sourced by BUFGs, PLL, and DCMs may enter a clock region. For further
information see the "Clock Resources" section in the S-6 User Guide.
Phase 6.30 Global Clock Region Assignment (Checksum:36e10472) REAL time: 4 mins 23 secs

 

That's because xst somehow changes my flipflops to an IDDR2 fixed in the wrong clock_region.

 

My code:

 

QF0 : FD_1
port map (
Q => QF(0), -- Data output
C => CLK270(0), -- Clock input
D => SI -- Data input
);
QF1 : FD_1
port map (
Q => QF(1), -- Data output
C => CLK270(1), -- Clock input
D => SI -- Data input
);
QF2 : FD_1
port map (
Q => QF(2), -- Data output
C => CLK270(2), -- Clock input
D => SI -- Data input
);
QF3 : FD_1
port map (
Q => QF(3), -- Data output
C => CLK270(3), -- Clock input
D => SI -- Data input
);

QR0 : FD
port map (
Q => QR(0), -- Data output
C => CLK270(0), -- Clock input
D => SI -- Data input
);
QR1 : FD
port map (
Q => QR(1), -- Data output
C => CLK270(1), -- Clock input
D => SI -- Data input
);
QR2 : FD
port map (
Q => QR(2), -- Data output
C => CLK270(2), -- Clock input
D => SI -- Data input
);
QR3 : FD
port map (
Q => QR(3), -- Data output
C => CLK270(3), -- Clock input
D => SI -- Data input
);

 

The failing xst result:

asi_lvds_rx.PNG

 

I tried lots of settings, attributes to keep the flip flops but no matter what, in my full design it's optimising to that IDDR2, depending on the settings sometime it's QR0_QF0 or QR1_QF1 or QR2_QF2 or QR3_QF3, one IDDR2 and six flip flops!

 

Here I have:

 

attribute syn_keep of QR:signal is TRUE;
attribute syn_keep of QF:signal is TRUE;

attribute iob of QF0:label is "FALSE";
attribute iob of QF1:label is "FALSE";
attribute iob of QF2:label is "FALSE";
attribute iob of QF3:label is "FALSE";

attribute iob of QR0:label is "FALSE";
attribute iob of QR1:label is "FALSE";
attribute iob of QR2:label is "FALSE";
attribute iob of QR3:label is "FALSE";

 

Thanks in advance for your help and suggestions!

Fabien

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Xilinx Employee
Xilinx Employee
13,929 Views
Registered: ‎09-20-2012

Re: Spartan 6 issue FD, FD_1 optimized to an IDDR2

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Hi,

 

When the IOB property is set to FALSE the tool has to not infer IDDR.

 

Can you try instantiating a LUT1 in between port and FF (to prevent IDDR inference)? Include KEEP or S constraint on the associated net to prevent trimming of LUT1.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
9,030 Views
Registered: ‎08-01-2008

Re: Spartan 6 issue FD, FD_1 optimized to an IDDR2

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Automatic clock placement is a two phase process. First, all clock components and their associated I/O components are placed, and then a second phase is run to constrain clock loads to locations that can be reached by the clock components. This usually involves area constraining the clock domains to one or more clock regions. 
 
In general, when automatic clock placement fails, the reason can be one of several things: 
- a poor selection was made for the clock component placement 
- a poor clock region allocation was made for one or more clock domains 
- the clock structure is very complex and a placement solution is difficult or impossible to find 
 
 To  work around for this and similar clock placement issues is to floorplan the clock components so that any such conflicts are avoided.

Thanks and Regards
Balkrishan
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9,027 Views
Registered: ‎03-15-2013

Re: Spartan 6 issue FD, FD_1 optimized to an IDDR2

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It's generating and fixing the IDDR2 in the wrong clock region compare to the bufhs that's why the automatic clock placement fails.

All my clocking is fixed and work.

As I said if I use bufgs instead of bufhs it's fine.

And bufhs works when I just implement asi rx to tx only.

But I want to keep my bufgs and use bufhs, the problem here is just this optmization to an IDDR2.

Due to that I have the automatic clock placement fails, I already analyzed the clocking and my plls, bufgs are defined.

I just need to prevent the tool to change the flip flops to an IDDR2!

Thanks

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Xilinx Employee
Xilinx Employee
13,930 Views
Registered: ‎09-20-2012

Re: Spartan 6 issue FD, FD_1 optimized to an IDDR2

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Hi,

 

When the IOB property is set to FALSE the tool has to not infer IDDR.

 

Can you try instantiating a LUT1 in between port and FF (to prevent IDDR inference)? Include KEEP or S constraint on the associated net to prevent trimming of LUT1.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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9,007 Views
Registered: ‎03-15-2013

Re: Spartan 6 issue FD, FD_1 optimized to an IDDR2

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Hi,

 

There is probably a problem with xst as I have the attribute iob false.

Anyway no error anymore with the lut.

The lut code if it helps someone...

 

  attribute keep of si_in     : signal is "TRUE";  
  attribute keep of si_buf    : signal is "TRUE";  

begin
    
       si_in <= SI;
       
       LUT_BUFFER : LUT1
       generic map (
          INIT => "10")
       port map (
          I0 => si_in,
          O => si_buf
       );   

asi_lvds_rx_ok.PNG

I'll have to see if it's working but at least it's compiling, mapped and fully routed!

 

Thanks.

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Xilinx Employee
Xilinx Employee
9,005 Views
Registered: ‎09-20-2012

Re: Spartan 6 issue FD, FD_1 optimized to an IDDR2

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Hi @fabien_vislink 

 

Good to know that it worked.

 

Feel free to post back here if you need any help.

 

Thanks,

Deepika.

Thanks,
Deepika.
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9,000 Views
Registered: ‎03-15-2013

Re: Spartan 6 issue FD, FD_1 optimized to an IDDR2

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Working on my hardware as well.

Thanks Deepika.

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1,156 Views
Registered: ‎03-07-2018

Re: Spartan 6 issue FD, FD_1 optimized to an IDDR2

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Hi!

Did you manage to implement the data recovery unit in spartan-6. I have been struggling a lot with it. it doesn't work at all.

 

could you help me please

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