02-15-2010 08:12 AM
Can anyone tell me if they have successfully interfaced an LX150 engineering sample Spartan6 with a 16bit DDR2 memory?
I have taken on a design featuring this combination. The memory IC is a Micron DDR2 part. There is an external VTT terminator with clean VREF source.
The board has been badly routed, and violates the MIG recommendations on track length matching etc. The track lengths range from about 38mm up to 62mm and the clocks aren't matched to data, nor are the DQS lines. It's a mess but I need to try and get the DDR2 to perform at >some< level.
Using the example project that the MIG spits out always see the same issue - in that after a set of writes followed by reads, only the last data to be written is returned.
Simulation using modelsim works fine(of course).
Power supplies are stable and in spec. I have tweaked the termination scheme in the UCF/Verilog to give best signal integrity (viewed on a decent 1GHz scope). I can see clean transitions through the reference levels, with little to no over/undershoot.
In terms of MIG I have implemented the ideas from answer records 34055, 34089, 34165
I have tried slowing the memory to its minimum (125MHz), slowed timings too.
I have also tried removing soft calibration and feeding in hard coded IDELAY values to compensate for my mismatched tracks.
Finally I have also disabled the built in test machine and replaced it with a really simple type.
I have an SP601 with a little LX16 on it and the MIG project works perfectly on that, but I don't know if this is true for the LX150 too.
If anyone has any experience of this part with MIG, or if anyone can think of areas I may not have exhausted I would love to hear from you.
RAM: Micron MT47H16M16-37e
ISE 11.4 with all packs/updates installed
02-15-2010 02:43 PM