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Visitor jbeesoniq1
Visitor
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Registered: ‎09-29-2008

Spartan6 IODELAY2 Calibration

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Hi,

 

In SP6 UG381 in the IODELAY2 section, subsection "Calibration Example" it states the following:

 

"In this example, the delay taps have an average value of 80 ps. An I/O clock of 250 MHz
(4,000 ps) is applied to IODELAY2. When the calibrate command is issued, a value of
4,000 / 80 = 50 is returned internally. If the input delay has been programmed to be
VARIABLE_FROM_HALF_MAX, then, following a reset command, the input delay value
is set to 25 taps, approximately ½ the input clock period."

 

Where did the avg of 80ps per tap come from?  According to the SP6 datasheet (ds162) Table 38 (IO Delay switiching charateristics) the average tap delay is more like 53ps at its highest, rather than 80ps.

 

Thanks!

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Visitor jbeesoniq1
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Registered: ‎09-29-2008

Re: Spartan6 IODELAY2 Calibration

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Teacher eteam00
Teacher
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Registered: ‎07-21-2009

Re: Spartan6 IODELAY2 Calibration

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According to the SP6 datasheet (ds162) Table 38 (IO Delay switiching charateristics) the average tap delay is more like 53ps at its highest, rather than 80ps.

 

Spartan-6 silicon was updated earlier this year, specifically to clean up the IODELAY blocks.  The current  version of DS162 reflects the latest and greatest IODELAY characterisation data.  The information you describe is in Table 39, which was updated in DS162 Version 1.3

 

The current version of UG381 (v1.4) pre-dates the IODELAY block revisions.  The Calibration Example description in UG381 is intended as a description of the IODELAY block calibration process, and is not meant to supercede the datasheet (DS162).  The datasheet numbers must be given precedence.

 

-- Bob Elkind

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Visitor jbeesoniq1
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Registered: ‎09-29-2008

Re: Spartan6 IODELAY2 Calibration

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Hi Bob,

 

Thank you for the clarification!  I have a mix of silicon from last year and this year, it sounds like they will operate differently?

 

I posted a separate question about not performing calibration for general async deskew for margin improvement(http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Skipping-Spartan6-IODELAY2-Cal/td-p/165848)... perhaps given this answer it is related.

 

 

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Teacher eteam00
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Registered: ‎07-21-2009

Re: Spartan6 IODELAY2 Calibration

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I have a mix of silicon from last year and this year, it sounds like they will operate differently?

 

Possibly, depending on wafer lots.  Answer Record 41083 speaks to this question.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor jbeesoniq1
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Registered: ‎09-29-2008

Re: Spartan6 IODELAY2 Calibration

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