02-19-2013 05:17 AM
For our project we need to establish communication between uC and FPGA clocked by its clock (named fClk).
The project is coded for SPARTAN-6 device, and the communication is based on a bi-directional bus used for write and read, and some control signals (nCS....) which are output only.
Along with the bus signals, the uC output the its bus clock (named bClk) for synchronization.
Since the uC signals are asynchronous to the FPGA and metastablity will probably occur, I tried to look out for bus synchronizer. I found topology that is based on sampling the bClk with two FF clocked by fClk and use an edge_detection circuit for detecting rising edges at bClk (Attached to post).
When I try to IMPLEMENT it in ISE, it warnings me that I use bCLk for non-clock input.
Is there any solution for it? Can I connect the bClk to FF D-input without warnings?
If not - can someone help me with helpful bus_synchronizer code??
I really need it.
ThanX in advance.
02-19-2013 06:52 AM
You should not get this warning unless you also use bClk as a clock. In the code you posted,
the only part where bClk is used as a clock was commented out. If you have an input pin
that is both a clock and a signal to the D of a flip-flop (in another clock domain) you should
instantiate the BUFG to drive the clocked processes, and use the unbuffered input for
the D input of the flip-flop. Otherwise the tools try to automatically insert a BUFG because
of the clock loads, and then without a separate name for the unbuffered signal, they try
to route that globally buffered clock signal to a D input of a flop, which is not a valid route
for Spartan 6.
02-19-2013 07:50 AM
U right, my mistake - the posted code should not have that comments. I added them when I debug the design. Without the comment I get that warnings as you say.
"If you have an input pin that is both a clock and a signal to the D of a flip-flop (in another clock domain) you should instantiate the BUFG to drive the clocked processes, and use the unbuffered input for
the D input of the flip-flop"
I agree. but how I write it to the syntesizer in the VHD file?
02-19-2013 12:38 PM
02-20-2013 01:55 AM
Following your advice, i changed some of the signal assignments in my code and added the BUFG instantiation.
It works now, and the implementation is good!
Thanks a lot!!