01-19-2015 04:01 AM
I am using two cascaded DCMs to generate 3 synchronous clocks:
My question is: Are the 3 generated clocks (clk, clk2x and clk4x) completely synchronous, completely phase aligned? If not, does Timing Analyzer consider the phase mismatch when calculating if PERIOD constraint is met?
I think that another design could be to use the CLKFX output to generate 'clk4x' clock:
In this case, I have exactly the same questions: Are the 3 generated clocks (clk, clk2x and clk4x) completely synchronous, completely phase aligned? If not, does Timing Analyzer consider the phase mismatch when calculating if PERIOD constraint is met?
Thanks a lot
01-19-2015 05:44 PM
Yes, the 3 clocks will be "nominally" in phase. The DCM is not perfect; there are phase errors both between the different output clocks (so clk and clk2x) and between the input and output clock (effectively between clkin and clkfbin). These phase errors are bounded, and (yes) are used to determine whether the paths between the clocks meet their respective PERIOD constraints.
When you cascade DCMs like the first example, these two phase errors add up, which makes it harder to meet the PERIOD constraint on the paths between clk and clk4x. The second example is better, since there is no addition of phase errors.
Also, the DCM adds jitter to the clock. When you cascade to DCMs, you add the jitter. Furthermore a DCM input can only tolerate a certain amount of jitter, so when you cascade them you have to be sure that the jitter output of the first is less than the jitter maximum that the 2nd one can take. It is (I think) generally not legal to cascade 3 DCMs in a row (the jitters are just too much), and depending on mode and frequency and your input clock jitter, even 2 may exceed the maximum jitter spec of the DCM.
So, for a number of reasons, it is better to have the three clocks coming out of the same DCM, rather than cascading them.