11-25-2010 01:39 AM - edited 11-25-2010 01:50 AM
I have a input signal to FPGA, Spartan 3A, the requirement is that the delay from FPGA pad to the first synchronous element should be no longer than 5ns, I did the FROM TO constraint,
TIMESPEC "TS_busy" = FROM PADS(busy) 5 ns;
However, this constriant can not be met, slack is around 0.2ns, I checked the P&R in FPGA Editor, the DFF connected to this input signal is not very closed to the pad.
How can I deal with it? I am not a veteran and never have had this kind of problem. Is there any Attribute to solve it? Or I have to work on placement manually, if yes, maybe I need to study the PlanAhead tool, right? Or I have to learn how to fix it in FPGA Editor? Or some other methord?
BTW, all the option in P&R tools are set to speed oriented or high level effort.
Any reply will be greatly appreciated. Thanks in advance.
11-25-2010 02:57 AM
Suggestion: Register the input signal in the IO block.
Use the synthesis attribute (* IOB="TRUE" *) for the instantiation of the register, to force the register location to an IOB.
- Bob Elkind
11-25-2010 06:54 PM
05-23-2013 09:51 AM
It happened to me this problem
Can be solved by re-install the program