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Registered: ‎08-31-2009

Timing constraint failed

I have a input signal to FPGA, Spartan 3A,  the requirement is that the delay from FPGA pad to the first synchronous element should be no longer than 5ns, I did the FROM TO constraint,

TIMESPEC "TS_busy" = FROM PADS(busy) 5 ns;

However, this constriant can not be met, slack is around 0.2ns, I checked the P&R in FPGA Editor, the DFF connected to this input signal is not very closed to the pad.


How can I deal with it? I am not a veteran and never have had this kind of problem. Is there any Attribute to solve it? Or I have to work on placement manually, if yes, maybe I need to study the PlanAhead tool, right? Or I have to learn how to fix it in FPGA Editor? Or some other methord?


BTW, all the option in P&R tools are set to speed oriented or high level effort.


Any reply will be greatly appreciated. Thanks in advance.

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3 Replies
Teacher eteam00
Registered: ‎07-21-2009

Re: Timing constraint failed

Suggestion:  Register the input signal in the IO block.


Use the synthesis attribute (* IOB="TRUE" *) for the instantiation of the register, to force the register location to an IOB.


- Bob Elkind

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Registered: ‎08-14-2007

Re: Timing constraint failed

I think the constraint you want is not a FROM : TO, but rather an OFFSET IN BEFORE constraint. This constrains the setup time to the clock, which includes the path from the data input to the first D flip-flop and takes into account clock delays. Theoretically this constraint should help get better timing. On the other hand , Bob's suggestion to place the flip-flop in the IOB is a good one. The only downside to that is that it may unnecessarily constrain the design and make it harder to meet the period constraint because of the longer routing on the output side of the first flop.
-- Gabor
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Registered: ‎05-23-2013

Re: Timing constraint failed

It happened to me this problem
Can be solved by re-install the program

God has power over all things
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