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sha@hys
Explorer
Explorer
10,843 Views
Registered: ‎05-31-2015

Using Cache addressible range as shared memory

Hello,

                        I was using LPDDR IC to load bss segment of application in xilinx SDK. I enabled cache in microblaze configuration in the address range for LPDDR for reduced execution time. The application was successfullly running at 20us. Now I am using same LPDDR memory's one portion as shared memory between SDK and VHDL code (using MPMC controller) and writing to LPDDR in address range not used by SDK application bss. I am reading out data written from VHDL side at SDK side and is getting only zero read. The cache is enabled and I am getting same execution time 20us (this time is critical) but the data is read out false. How can I make it correct? When I did not enable cache I got correct data read with same SDK and VHDL code but my execution time of SDK is so high which is not acceptable. Also people at my place insist in using LPDDR (not BRAM) as we have huge chunks of data. BRAM can be configured in spartan 6 for memory size of 64 KB or something only. My LPDDR size is 64MB.Please help.

 

 

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sha@hys
Explorer
Explorer
10,277 Views
Registered: ‎05-31-2015

Hello,

 

 

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sha@hys
Explorer
Explorer
10,276 Views
Registered: ‎05-31-2015

Hello,

 

Finally I decided touse BRAM as shared memory.

 

 

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