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marcoh
Visitor
Visitor
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Registered: ‎03-26-2011

Using PLL in Spartan 6 device

Hi,

 

I've got a little question about the power supply for the Spartan 6 devices. Does I need a special supply for the PLL's or is the PLL powered by a standard supply? I've read the manuals, but I did not found this information.

 

My other problem is that I'm not sure whether I can route every global clock input internally to both of the two PLL's or do I need to use a special global clock input pin for a special PLL?

 

Thank you a lott for your help

 

Marco

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2 Replies
austin
Scholar
Scholar
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Registered: ‎02-27-2008

Marco,

 

No, the PLL is supplied from the exisiting power to the FPGA device.

 

Consult the user's guide for restrictions on clock pin placement vs. PLL location.

 

http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

 

pg 109

Austin Lesea
Principal Engineer
Xilinx San Jose
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eteam00
Professor
Professor
2,794 Views
Registered: ‎07-21-2009


@austin.lesea wrote:

Consult the user's guide for restrictions on clock pin placement vs. PLL location.

http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

pg 109


I think the section to which Austin is referring is on page 106, not page 109.

Current UG382 is version 1.5

 

-- Bob Elkind

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