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Visitor
Visitor
75,650 Views
Registered: ‎12-09-2010

Verilog - Variable bit range selection

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Hello,

 

I have the following code: (simplified a bit)

    reg [N:0] j;
    always@ (negedge clk) begin
        for (j=1; j<N-1; j=j+1) begin
            a[j+1][N-1:j+1] <= a[j][N-1:j+1];
            b[j+1][N-1:j+1] <= b[j][N-1:j+1];


            s[j][j:0] <= {sum[j], s[j-1][j-1:0]};
        end
    end

 

And I get the following errors:

ERROR:HDLCompilers:110 - "pipelinedAdder8bit.v" line 67 Least significant bit operand in part-select of word-select of vector reg array 'a' is illegal
ERROR:HDLCompilers:106 - "pipelinedAdder8bit.v" line 67 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:110 - "pipelinedAdder8bit.v" line 67 Least significant bit operand in part-select of word-select of vector reg array 'a' is illegal
ERROR:HDLCompilers:107 - "pipelinedAdder8bit.v" line 67 Illegal right hand side of nonblocking assignment
ERROR:HDLCompilers:110 - "pipelinedAdder8bit.v" line 68 Least significant bit operand in part-select of word-select of vector reg array 'b' is illegal
ERROR:HDLCompilers:106 - "pipelinedAdder8bit.v" line 68 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:110 - "pipelinedAdder8bit.v" line 68 Least significant bit operand in part-select of word-select of vector reg array 'b' is illegal
ERROR:HDLCompilers:107 - "pipelinedAdder8bit.v" line 68 Illegal right hand side of nonblocking assignment
ERROR:HDLCompilers:109 - "pipelinedAdder8bit.v" line 70 Most significant bit operand in part-select of word-select of vector reg array 's' is illegal
ERROR:HDLCompilers:106 - "pipelinedAdder8bit.v" line 70 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:109 - "pipelinedAdder8bit.v" line 70 Most significant bit operand in part-select of word-select of vector reg array 's' is illegal
ERROR:HDLCompilers:107 - "pipelinedAdder8bit.v" line 70 Illegal right hand side of nonblocking assignment

 

I found the following post about multiple variables being used to select bit ranges:

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Verilog-coding/m-p/94588

 

However, it appears you cant have more than one 'equated' value in a multidimensional array as even this line of code will not work as errors are produced on both sides of the none blocking equals:

s[j][j:0] <= {sum[j], s[j-1][j-1:0]};

 

I was hoping somebody has some advice on where I could go from here to get around this limitation.

 

Thanks

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Professor
Professor
105,247 Views
Registered: ‎08-14-2007

Re: Verilog - Variable bit range selection

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The errors in both cases you showed have to do with a variable number of bits

in the range.  Verilog assignments _must_ have a range that evaluates to a

constant number of bits.  So if "j" is not a constant (i.e. as in your case it's

a loop variable) then [j:0] is not legal because it evaluates to a different number

of bits depending on the value of "j".  Verilog is also strict about the syntax for

bit selects when there are multiple bits selected.  You cannot have [j:j-5] even

though that evaluates to a constant number of bits.  Basically for a variable bit

select your only choices are:

 

1) Single bit:

foo[j]

 

2) Multiple bit with size:

foo[j +: 3] or foo [j -: 3]

 

If your code doesn't fit into either category, you can add another loop dimension

to sequence through the bits:

 

for (j = 0; j < 6;j = j + 1)

  for (i = 0;i < N; i = i + 1)

    if (i > j) foo[i] <= bar[i];

 

In the above example you have a different number of bits of bar copied into foo

in each iteration of the outer loop.

 

-- Gabor

-- Gabor

View solution in original post

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Xilinx Employee
Xilinx Employee
75,643 Views
Registered: ‎09-07-2009

Re: Verilog - Variable bit range selection

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Hi Lekker,

  This is fully C style. You'd better not write the code like this.

  Always think about the circuit. How can the circuit assign all these data in one clock?

  I don't think this is necessary. You must have other ways to make your design.

  If you want to do a array, use RAM inside FPGA.

Binx

Highlighted
Professor
Professor
105,248 Views
Registered: ‎08-14-2007

Re: Verilog - Variable bit range selection

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The errors in both cases you showed have to do with a variable number of bits

in the range.  Verilog assignments _must_ have a range that evaluates to a

constant number of bits.  So if "j" is not a constant (i.e. as in your case it's

a loop variable) then [j:0] is not legal because it evaluates to a different number

of bits depending on the value of "j".  Verilog is also strict about the syntax for

bit selects when there are multiple bits selected.  You cannot have [j:j-5] even

though that evaluates to a constant number of bits.  Basically for a variable bit

select your only choices are:

 

1) Single bit:

foo[j]

 

2) Multiple bit with size:

foo[j +: 3] or foo [j -: 3]

 

If your code doesn't fit into either category, you can add another loop dimension

to sequence through the bits:

 

for (j = 0; j < 6;j = j + 1)

  for (i = 0;i < N; i = i + 1)

    if (i > j) foo[i] <= bar[i];

 

In the above example you have a different number of bits of bar copied into foo

in each iteration of the outer loop.

 

-- Gabor

-- Gabor

View solution in original post

Highlighted
Visitor
Visitor
75,612 Views
Registered: ‎12-09-2010

Re: Verilog - Variable bit range selection

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Hi Binx,

 

I am very new to Verilog, and still have not fully grasped how a lot of code is synthesized.

 

This is supposed to be a pipline. With every clock, the a and b registers get dumped into the registers of the next stage. The low order bits of a and b go into a full adder. The sum from the full adder becomes the high order bit of the s register. I have included a basic diagram of what my code is doing. There are carry registers between each  full adder which are not shown.

 

PiplinedAdder

 

I was under the impression that Verilog would unwrap the loop I have in my previous post, which will result in the diagram I have included.

 

Please correct me if I am wrong.

 

Thanks

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Visitor
Visitor
75,607 Views
Registered: ‎12-09-2010

Re: Verilog - Variable bit range selection

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Gabor,

 

You are a genious! I just read your post, and that is exactly what I need.

 

I still want to verify that in the code in my first post, Verilog will 'unwrap' the loop I have, and my reg j will actually disapear?

 

Thanks

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Mentor
Mentor
75,601 Views
Registered: ‎11-29-2007

Re: Verilog - Variable bit range selection

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You are a genious! I just read your post, and that is exactly what I need.

If that is the case, then mark his post as solution and consider giving him kudos.

 

 

 


I still want to verify that in the code in my first post, Verilog will 'unwrap' the loop I have, and my reg j will actually disapear?

 

Yes, no resources will by spent on j.

 

 

Adrian



Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).
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Professor
Professor
75,596 Views
Registered: ‎08-14-2007

Re: Verilog - Variable bit range selection

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Yes, loops are always unwrapped (I usually say "unrolled") in hardware.  To drive

the point home, I would normally declare the loop variable as an "integer" which is

something I never use for hardware registers.  The other thing commonly done for

loop index variables is to make them local to the process like:

 

always @ (posedge clk or posedge rst)

begin : Proc_name // block must be named to allow local declarations

  integer i

  if (rst)

    begin

      reset assignments go here

    end

  else

    begin

      clock edge assignments go here

      for (i = 0; i < N;i = i + 1) . . .

    end

end // Proc_name

 

In this example template, "i" is only available within the block named "Proc_name".

 

-- Gabor

-- Gabor
Highlighted
Visitor
Visitor
75,584 Views
Registered: ‎12-09-2010

Re: Verilog - Variable bit range selection

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Thanks guys!

 

I am taking a Verilog course right now at university. My proffesor has delved into a lot of circuit logic, but has failed to really disguss details of Verilog and how it is synthesized, so I really appreciate this.

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Newbie
Newbie
73,875 Views
Registered: ‎02-02-2012

Re: Verilog - Variable bit range selection

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hi ..

 

i'm trying to implement sliding dictionary algorithm on FPGA

 

while writing the code i found myself to use variable range bit selections

 

i cant do it properly

 

the theme of the processing is to compare 2 parts of asingle  variable lets say buffer and assign values to other variables accordingly 

 

can you guys please help me with this ?

 

i tried the above two loop sequence but i just cant get it right ..

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Instructor
Instructor
73,873 Views
Registered: ‎07-21-2009

Re: Verilog - Variable bit range selection

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zinxy,

 

This subject is completely unrelated to this thread.  Plesae start a new thread in the General Technology forum.  That is where you are likely to attract helpful responses.

 

Posting an unrelated topic to an existing thread is considered rude, and I am sure that is not your intent.

 

Thank you for your consideration.

 

-- Bob Elkind

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Highlighted
16,784 Views
Registered: ‎02-27-2013

Re: Verilog - Variable bit range selection

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hey can you just tell me in which tool you are using this clock cyle

 

 

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