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pofeng1885
Contributor
Contributor
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Registered: ‎04-06-2011

What's the initial value of the Register in Spartan6 Device when poweron??

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I want to know the initial value of registers in FPGA device when power is on. And how to set it? In verilog/VHDL  or ISE ?

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eteam00
Instructor
Instructor
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Registered: ‎07-21-2009

In the ISE Navigator shell, open up the Language Templates by clicking on the lightbulb icon.

 

Language Templates are listed for both VHDL and Verilog.

Using Verilog as an example, navigate through the Language Templates as follows:

 

Verilog > Synthesis Constructs > Signal, Constant, & Variable Declarations > Register > Initialized > Reg > 16-bit

 

And here is the template:  reg [15:0] <name> = 16'h0000;

 

The assigned value can be any value which matches the width of the declared reg.  The initialisation takes place as part of the FPGA configuration process.  If your only need for a reset signal is to initialise state, use of the assigned initial value could remove the need for an instantiated reset in the design, which means fewer hardware resources used in your design.

 

Make sense?  Have fun with the templates, they are very handy and informative.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

4 Replies
eteam00
Instructor
Instructor
5,785 Views
Registered: ‎07-21-2009

In the ISE Navigator shell, open up the Language Templates by clicking on the lightbulb icon.

 

Language Templates are listed for both VHDL and Verilog.

Using Verilog as an example, navigate through the Language Templates as follows:

 

Verilog > Synthesis Constructs > Signal, Constant, & Variable Declarations > Register > Initialized > Reg > 16-bit

 

And here is the template:  reg [15:0] <name> = 16'h0000;

 

The assigned value can be any value which matches the width of the declared reg.  The initialisation takes place as part of the FPGA configuration process.  If your only need for a reset signal is to initialise state, use of the assigned initial value could remove the need for an instantiated reset in the design, which means fewer hardware resources used in your design.

 

Make sense?  Have fun with the templates, they are very handy and informative.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

pofeng1885
Contributor
Contributor
4,512 Views
Registered: ‎04-06-2011
Hi Bob ,
Thanks for your quickly reply..I got it.
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gszakacs
Professor
Professor
4,499 Views
Registered: ‎08-14-2007

Here's some more points:

 

When you don't give an initial value to a register by any other means it defaults to zero.

However in that case, your design will not match simulation, wich initialized the

registers to "unknown."

 

If a register has an asynchronous or synchronous reset as part of the behavioral

description, then the value it is assigned for reset will also be the initial value

of the register.

 

i.e.

 

reg [15:0] foo = 16'h1234; // Explicitly declared init value

 

or:

 

reg [16:0] foo; // no init value in the declaration

 

always @ (posedge clk or posedge rst)

  if (rst) foo <= 16'h1234;  // XST will use this as the init value

  else foo <= bar;

 

or:

 

reg [16:0] foo;

 

initial foo = 16'h1234;

 

in all three cases foo will start up as 0x1234.

 

but:

 

reg [15:0] foo;  // no init value declared

 

always @ (posedge clk) foo <= bar;

 

In this case foo will initialize to zero for synthesis, but to 16'hXXXX for simulation.

 

-- Gabor

-- Gabor
pofeng1885
Contributor
Contributor
4,483 Views
Registered: ‎04-06-2011
Hi gszakacs
Thanks for your sharing....

--Pofeng
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