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Visitor likesky
Visitor
3,043 Views
Registered: ‎06-16-2015

error in using two instances of the X1 SRIO core in my application

i use two instance of x1 mode SRIO, but i have error in ucf file, here is my code

NET "srio_txp0" LOC = B4;
NET "srio_txn0" LOC = A4;
NET "srio_rxp0" LOC = D5;
NET "srio_rxn0" LOC = C5;
NET "sys_clkp" LOC = B8 ; # MGT101
NET "sys_clkn" LOC = A8 ; # MGT101
NET "srio_txp1" LOC = B6;
NET "srio_txn1" LOC = A6;
NET "srio_rxp1" LOC = D7;
NET "srio_rxn1" LOC = C7;
NET "sys_clkp1" LOC = D9 ; # MGT101
NET "sys_clkn1" LOC = C9 ; # MGT101
INST "u_camera_process/inst_test_srio_top/rio_de_wrapper/phy_wrapper_inst/srio_gt_wrapper/gtp_wrapper_i/tile0_gtp_wrapper_i/gtpa1_dual_i" LOC = "GTPA1_DUAL_X0Y0";# lane0	
INST "u_camera_process/inst_test_srio_top/phy_1x_ser_clk/u_refclk_ibufds" IOSTANDARD = LVDS_25;
NET "u_camera_process/inst_test_srio_top/UCLK"      TNM_NET = "UCLK";
NET "u_camera_process/inst_test_srio_top/UCLK2"      TNM_NET = "UCLK2";
NET "u_camera_process/inst_test_srio_top/LNK_CLK"      TNM_NET = "LNK_CLK";		
# For GTP operation at 1.25 GHz
TIMESPEC "TS_UCLK"    = PERIOD "UCLK"  16.0 ns HIGH 50 % INPUT_JITTER 100 ps PRIORITY 0;
TIMESPEC "TS_UCLK2" = PERIOD "UCLK2" "TS_UCLK" / 2 HIGH 50 % INPUT_JITTER 100 ps PRIORITY 1;
TIMESPEC "TS_LNK_CLK" = PERIOD "LNK_CLK" "TS_UCLK" * 4 HIGH 50 % INPUT_JITTER 100 ps PRIORITY 1;

INST "u_camera_process/inst_test_srio_top_1/rio_de_wrapper/phy_wrapper_inst/srio_gt_wrapper/gtp_wrapper_i/tile0_gtp_wrapper_i/gtpa1_dual_i" LOC = "GTPA1_DUAL_X0Y0";# lane0	
INST "u_camera_process/inst_test_srio_top_1/phy_1x_ser_clk/u_refclk_ibufds" IOSTANDARD = LVDS_25;
NET "u_camera_process/inst_test_srio_top_1/UCLK"      TNM_NET = "UCLK1";
NET "u_camera_process/inst_test_srio_top_1/UCLK2"      TNM_NET = "UCLK21";
NET "u_camera_process/inst_test_srio_top_1/LNK_CLK"      TNM_NET = "LNK_CLK1";		
# For GTP operation at 1.25 GHz
TIMESPEC "TS_UCLK1"    = PERIOD "UCLK1"  16.0 ns HIGH 50 % INPUT_JITTER 100 ps PRIORITY 0;
TIMESPEC "TS_UCLK21" = PERIOD "UCLK21" "TS_UCLK1" / 2 HIGH 50 % INPUT_JITTER 100 ps PRIORITY 1;
TIMESPEC "TS_LNK_CLK1" = PERIOD "LNK_CLK1" "TS_UCLK1" * 4 HIGH 50 % INPUT_JITTER 100 ps PRIORITY 1;

and the error is

ERROR:Pack:2811 - Directed packing was unable to obey the user design
   constraints (LOC=GTPA1_DUAL_X0Y0) which requires the combination of the
   symbols listed below to be packed into a single GTPA1_DUAL component.

 so, i do not how to solve this error.

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4 Replies
Visitor likesky
Visitor
2,928 Views
Registered: ‎06-16-2015

回复: error in using two instances of the X1 SRIO core in my application

please help, i canot solve this error

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Xilinx Employee
Xilinx Employee
2,921 Views
Registered: ‎02-06-2013

Re: error in using two instances of the X1 SRIO core in my application

Hi

 

It looks you have same (LOC=GTPA1_DUAL_X0Y0) constraint for both the instances, Can you re check this?

Regards,

Satish

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Visitor likesky
Visitor
2,910 Views
Registered: ‎06-16-2015

Re: error in using two instances of the X1 SRIO core in my application

i use xc6slx25T,there is only one GTP_DUAL,which contains 2 lanes, so i want to use these 2 lanes, they are all in X0Y0

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Visitor likesky
Visitor
2,909 Views
Registered: ‎06-16-2015

Re: error in using two instances of the X1 SRIO core in my application

I use lane0 to implement 1x srio and it work, i can generate bitstream,as follows

NET "srio_txp0" LOC = B4;
NET "srio_txn0" LOC = A4;
NET "srio_rxp0" LOC = D5;
NET "srio_rxn0" LOC = C5;
NET "sys_clkp" LOC = B8 ; # MGT101
NET "sys_clkn" LOC = A8 ; # MGT101
INST "u_camera_process/inst_test_srio_top/rio_de_wrapper/phy_wrapper_inst/srio_gt_wrapper/gtp_wrapper_i/tile0_gtp_wrapper_i/gtpa1_dual_i" LOC = "GTPA1_DUAL_X0Y0";# lane0
INST "u_camera_process/inst_test_srio_top/phy_1x_ser_clk/u_refclk_ibufds" IOSTANDARD = LVDS_25;
NET "u_camera_process/inst_test_srio_top/UCLK" TNM_NET = "UCLK";
NET "u_camera_process/inst_test_srio_top/UCLK2" TNM_NET = "UCLK2";
NET "u_camera_process/inst_test_srio_top/LNK_CLK" TNM_NET = "LNK_CLK";
# For GTP operation at 1.25 GHz
TIMESPEC "TS_UCLK" = PERIOD "UCLK" 16.0 ns HIGH 50 % INPUT_JITTER 100 ps PRIORITY 0;
TIMESPEC "TS_UCLK2" = PERIOD "UCLK2" "TS_UCLK" / 2 HIGH 50 % INPUT_JITTER 100 ps PRIORITY 1;
TIMESPEC "TS_LNK_CLK" = PERIOD "LNK_CLK" "TS_UCLK" * 4 HIGH 50 % INPUT_JITTER 100 ps PRIORITY 1;

 

but when i only change the location of T/RX/CLK_P/N from lane0 to lane 1,it report error:

 

NET "srio_txp0" LOC = B6;
NET "srio_txn0" LOC = A6;
NET "srio_rxp0" LOC = D7;
NET "srio_rxn0" LOC = C7;
NET "sys_clkp" LOC = D9 ; # MGT101
NET "sys_clkn" LOC = C9 ; # MGT101
INST "u_camera_process/inst_test_srio_top/rio_de_wrapper/phy_wrapper_inst/srio_gt_wrapper/gtp_wrapper_i/tile0_gtp_wrapper_i/gtpa1_dual_i" LOC = "GTPA1_DUAL_X0Y0";# lane0
INST "u_camera_process/inst_test_srio_top/phy_1x_ser_clk/u_refclk_ibufds" IOSTANDARD = LVDS_25;
NET "u_camera_process/inst_test_srio_top/UCLK" TNM_NET = "UCLK";
NET "u_camera_process/inst_test_srio_top/UCLK2" TNM_NET = "UCLK2";
NET "u_camera_process/inst_test_srio_top/LNK_CLK" TNM_NET = "LNK_CLK";
# For GTP operation at 1.25 GHz
TIMESPEC "TS_UCLK" = PERIOD "UCLK" 16.0 ns HIGH 50 % INPUT_JITTER 100 ps PRIORITY 0;
TIMESPEC "TS_UCLK2" = PERIOD "UCLK2" "TS_UCLK" / 2 HIGH 50 % INPUT_JITTER 100 ps PRIORITY 1;
TIMESPEC "TS_LNK_CLK" = PERIOD "LNK_CLK" "TS_UCLK" * 4 HIGH 50 % INPUT_JITTER 100 ps PRIORITY 1;

 

ERROR:Place:1073 - Placer was unable to create RPM[GTP_RPMs] for the component
u_camera_process/inst_test_srio_top/rio_de_wrapper/phy_wrapper_inst/srio_gt_w
rapper/gtp_wrapper_i/tile0_gtp_wrapper_i/gtpa1_dual_i of type GTP_DUAL for
the following reason.
The reason for this issue:
All of the logic associated with this structure is locked and the relative
placement of the logic violates the structure. The problem was found between
the relative placement of GTP_DUAL
u_camera_process/inst_test_srio_top/rio_de_wrapper/phy_wrapper_inst/srio_gt_w
rapper/gtp_wrapper_i/tile0_gtp_wrapper_i/gtpa1_dual_i at site GTPA1_DUAL_X0Y0
and OPAD srio_txp0 at site OPAD_X0Y0. The following components are part of
this structure:
GTP_DUAL
u_camera_process/inst_test_srio_top/rio_de_wrapper/phy_wrapper_inst/srio_gt_w
rapper/gtp_wrapper_i/tile0_gtp_wrapper_i/gtpa1_dual_i
OPAD srio_txp0

 

so, i am confused, i don't know where is wrong.

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