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Visitor kanwal_
Visitor
36,808 Views
Registered: ‎05-05-2012

how to instantiate ODDR block?

hi

please tell me how to instantiate ODDR block to remov DCM clocking error 1203 in spartan 6......plz urgently give me the ans?

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13 Replies
Explorer
Explorer
36,805 Views
Registered: ‎07-24-2011

Re: how to instantiate ODDR block?

Teacher eteam00
Teacher
36,798 Views
Registered: ‎07-21-2009

Using ODDR for Clock forwarding

If you reference a specific error message code, you should include the text of the error message in your post.  I am not familiar with "DCM clocking error 1203".

 

If the question is:

 

How do I forward an internal global clock to an output pin?

 

the answer is an approach which is

  • well documented
  • applies (generally) to all FPGA families
  • called 'clock forwarding'

 

Specifically, try the following:

  • Open ISE
  • Click on the 'light bulb' icon to bring up the Language Templates window
  • Follow Verilog (or VHDL)>Synthesis Constructs>Coding Examples>Misc>Output Clock Forwarding Using DDR
  • Read the Info section, as well as the family-specific sections

 

For Verilog and Spartan-6, you will find the following example:

 

   // Clock forwarding circuit using the double data-rate register
   //        Spartan-3E/3A/6
   // Xilinx HDL Language Template, version 13.4

   ODDR2 #(
      .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
      .INIT(1'b0),    // Sets initial state of the Q output to 1'b0 or 1'b1
      .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
   ) clock_forward_inst (
      .Q(<output_clock>),     // 1-bit DDR output data
      .C0(<internal_clock>),  // 1-bit clock input
      .C1(~<internal_clock>), // 1-bit clock input
      .CE(<stop_clock>),      // 1-bit clock enable input
      .D0(1'b0), // 1-bit data input (associated with C0)
      .D1(1'b1), // 1-bit data input (associated with C1)
      .R(<hold_clock_low>),   // 1-bit reset input
      .S(<hold_clock_high>)   // 1-bit set input
   );

   // End of clock_forward_inst instantiation

 

The following example showing clock forwarding to an output pin is edited from UG382, Figure 3-13:

forums_clock-forwarding-with-ODDR.PNG

 

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Visitor kanwal_
Visitor
36,761 Views
Registered: ‎05-05-2012

Re: Using ODDR for Clock forwarding

hi, thanks for your quick response ...,,,

 

//actually i made a following verilog program

module (clk_in,clk_out1,clk_out2)
input clk_in; output clk_out1,clk_out2;
// instantiate dcm
mydcm 1 (
  .CLK_IN1(clk_in1),
  .CLK_OUT1(clk_out1), // same as input clk
  .CLK_OUT2(clk_out2)  // clk2x
 );
endmodule

during mapping i get following error :
"ERROR:Place:1136 - This design contains a global buffer instance,
   <uut/clkout1_buf>, driving the net, <CLK_OUT1_OBUF>, that is driving the
   following (first 30) non-clock source pins.
   < PIN: CLK_OUT1.O; >"


to solve this problem i add oddr2 in my prog but still get the same error please help me to solve this problem

i shall be very thankful to you.

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Visitor aliaarshad
Visitor
36,757 Views
Registered: ‎05-06-2012

"clock_forward_inst" failed to join the "OLOGIC2" component as required.

hi,

i tried to instantiate oddr2 in my verilog program bt during mapping it gives the following error

 

 

Pack:2531 - The dual data rate register "clock_forward_inst" failed to
join the "OLOGIC2" component as required. The output signal for register
symbol clock_forward_inst requires general routing to fabric, but the
register can only be routed to ILOGIC, IODELAY, and IOB.
ERROR:Pack:2531 - The dual data rate register "clock_forward_inst" failed to
join the "OLOGIC2" component.

 

how to overcome this problem?

i will be very thankful for your response.

 

thanks

aliya

Tags (1)
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Teacher eteam00
Teacher
36,750 Views
Registered: ‎07-21-2009

please start a new thread

Aliya, please start a new thread to discuss your separate problem.  This thread is for discussing kanwal's design.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Teacher eteam00
Teacher
36,749 Views
Registered: ‎07-21-2009

Re: Using ODDR for Clock forwarding

Kanwal,

 

You have signals connected improperly, including a clock signal driving non-clock pins.  If you cannot fix this on your own, then please post your source code which includes all clock signal connections and references.

 

A BUFG output cannot drive an OBUF input directly.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Xilinx Employee
Xilinx Employee
36,744 Views
Registered: ‎07-01-2008

Re: "clock_forward_inst" failed to join the "OLOGIC2" component as required.

The ODDR in the OLOGIC component has very limited connectivity. Usually it should be driving a single output buffer. The error message indicates your ODDR is driving fabric logic which cannot be supported.

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Highlighted
Observer suresh007
Observer
31,878 Views
Registered: ‎05-21-2013

Re: Using ODDR for Clock forwarding

hi sir,

 

its fine with spartan6

 

can you please help me out in KINTEX 7BOARD

 

 

CLOCKING_WIZARD--------->ODDR------>OBUF-------->GPIOPIN(Y23)

 

idea is to check the clock perfomance on the pin

 

please do correct me if Im wrong

 

Any help will be highly appreciable !!!!!!!!!

 

 

Thanks in advance

 

Regards

Suresh

Tags (1)
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Newbie jagsshete
Newbie
29,321 Views
Registered: ‎07-08-2014

Re: "clock_forward_inst" failed to join the "OLOGIC2" component as required.

ERROR:Pack:2531 - The dual data rate register "DCM1/clock_3" failed to join the
"OLOGIC2" component as required. The output signal for register symbol
DCM1/clock_3 requires general routing to fabric, but the register can only be
routed to ILOGIC, IODELAY, and IOB.
ERROR:Pack:2530 - The dual data rate register "DCM1/clock_1" failed to join an
OLOGIC component as required.

 

 

plese help me ....

 

DCM for spartan 6 lx 45 device is but it gives erroe 1130 but it eleminated by using ODDR2. DCM output given to ODDR2 but it gives above error. 

 

suggest me solution..

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Newbie jagsshete
Newbie
5,507 Views
Registered: ‎07-08-2014

Re: "clock_forward_inst" failed to join the "OLOGIC2" component as required.

ERROR:Pack:2531 - The dual data rate register "DCM1/clock_3" failed to join the
"OLOGIC2" component as required. The output signal for register symbol
DCM1/clock_3 requires general routing to fabric, but the register can only be
routed to ILOGIC, IODELAY, and IOB.
ERROR:Pack:2530 - The dual data rate register "DCM1/clock_1" failed to join an
OLOGIC component as required.

 

 

plese help me ....

 

DCM for spartan 6 lx 45 device is selected  but it gives error 1130 but it eleminated by using ODDR2. DCM output given to ODDR2 but it gives above error. 

 

suggest me solution..

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Visitor mkjaswal
Visitor
3,178 Views
Registered: ‎03-27-2017

Re: "clock_forward_inst" failed to join the "OLOGIC2" component as required.

hey anyone found any solution to this PLEASE!!!

MKJ
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Community Manager
Community Manager
3,157 Views
Registered: ‎08-08-2007

Re: "clock_forward_inst" failed to join the "OLOGIC2" component as required.

Hi @mkjaswal,

 

In our Help Page there is a tip 

Tip: If the message is older than 6-12 months, please post a new message rather than adding to the existing thread. Your inquiry will have a better chance of being picked up by an expert if it is a new topic.

https://forums.xilinx.com/t5/help/faqpage/faq-category-id/posting#posting

 

This question is 3 years old with 11 replies so you will probably get more traction if you create a new post with your question.

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Visitor mkjaswal
Visitor
3,140 Views
Registered: ‎03-27-2017

Re: "clock_forward_inst" failed to join the "OLOGIC2" component as required.

@sandrao   ok i will do it

MKJ
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