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11,639 Views
Registered: ‎12-18-2010

n00b question about cores vs VHDL for ethernet

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forgive my ignorance but I'm a n00b to FPGA coming from a software background.

 

Just like 5000 other n00b posters on this form, I want to use the ethernet capabilities of my spartan-3e. Nobody online actually has a ready-made copy/paste solution for this, and that's ok by me. I'll do the work and figure it out. I've already done a lot of the homework, but I'm confused about one thing in general...

 

I'm aware that there are two fundamental ways to use the ethernet controller: using the free IP core that xilinx's IDE offers, or writing VHDL/verilog myself and correctly banging out an MII interface. The latter method is a royal pain apparently because you have to calculate checksums and otherwise manipulate TCP/UDP packets at about the lowest level possible...

 

My question is this: My application requires packets to be processed with the lowest amount of overhead possible. I don't even want to have to wait one extra clock cycle if I don't have to. My understand was that any *core* that you put on an FPGA is effectively a "soft-core" processor, in other words, the robust functionality from these various IP cores exists because the FPGA is programmed with VHDL instructions that simulate, say, an 8086 CPU  that basically run a program written in C or assembly for this virtual 8086, since it's a lot easier to use these languages than VHDL. Is that correct ? If so, does that mean I would expect my overall network performance to be slower than if I wrote the processing myself in straight-vhdl ?

 

If not, then can a "core" coexist with a straight VHDL program, the same way as I would link to an external symbol in C ? Or does the core consume the whole chip ?

 

Thank you for taking the time to respond to a n00b. I appreciate it.

 

-n00b

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46 Replies
rcingham
Teacher
Teacher
7,546 Views
Registered: ‎09-09-2010

 


@eteam00 wrote:

Adrian, that was quite droll.  I like it.  This is a side of you we've not yet seen.

 

I should add droll wit to my list of character attributes required of all FPGA designers.

 

- Bob Elkind


 

And not "shining wit", then?

:smileywink:


------------------------------------------
"If it don't work in simulation, it won't work on the board."
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eteam00
Professor
Professor
7,544 Views
Registered: ‎07-21-2009

And not "shining wit", then?

You are welcome to start your own list, but I think droll exudes a low-key self-confidence which is most becoming to FPGA designers.  Shining is a bit too flashy for my tastes.  Software types might show shining wit, while we FPGA designers will take on a more subdued and less ostentatious demeanour.  We shall refuse to preen.

 

Well, my esteemed colleagues, what say you?

 

- Bob Elkind

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awillen
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Registered: ‎11-29-2007

Actually, I'm as much a software guy as I'm a hardware guy. Deep in my heart, I'm the optimization type – and that spans software and hardware :smileyhappy:

 

 



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eteam00
Professor
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Registered: ‎07-21-2009

Actually, I'm as much a software guy as I'm a hardware guy. Deep in my heart, I'm the optimization type – and that spans software and hardware :smileyhappy:

And that makes you...  half shiny and half droll?

 

Sorry, your wit and your writings betray you.  You are undoubtedly an FPGA designer at your core.  You can't possibly convince me otherwise.  Your protests to the contrary will fall on deaf, elitist ears!  :)

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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bassman59
Historian
Historian
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Registered: ‎02-25-2008

 


@awillen wrote:

 


Whether they are useful for production designs is an exercise that's unfortunately left up to the engineer (short answer: generally, no, they are not useful for production designs).

I'm curious: why not?

 


 

Ah, you haven't had the misfortune of trying to actually use the Xilinx gigabit Ethernet core ...

----------------------------Yes, I do this for a living.
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awillen
Mentor
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7,523 Views
Registered: ‎11-29-2007

 


And that makes you...  half shiny and half droll?

A shiny dtroll?

 

 

 


You can't possibly convince me otherwise.  Your protests to the contrary will fall on deaf, elitist ears!  :)

 

That must be caused by the hardware design stuff, since allegedly we all share that trait.

 

 

Adrian



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eteam00
Professor
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Registered: ‎07-21-2009

And that makes you...  half shiny and half droll?


A shiny dtroll?

dtroll?  is that metric eurospeak for demi-droll, as in half-droll?

 

What is the other half of a demi-droll, an ashton-droll?    (used to be a bruce-droll) ?

 

-- Bob "random" Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
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7,478 Views
Registered: ‎12-18-2010

Just an update, inserted wishbone open-source TCP/IP code and lo and behold, I'm stopped dead in my tracks by another bug in the toolchain. what a surprise.

 

Mapping all equations...
ERROR:Xst:2033 - Port I of Input buffer infrastructure_top0/SINGLE_ENDED_CLKS_INST.SYS_CLK_INST is connected to GND
ERROR:Xst:1847 - Design checking failed

 

when searching for this error, they claim it started in ISE 8.1, yet I'm building this on version 10.1.03. So apparently they had better things to do than fix it. They were probably too busy writing 50-line legalese comments in their VHDL code about copyright, or maybe finding new and fun ways to limit the functionality of or restrict access to the evaluation IP cores. anything but improve quality, huh ?

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mcgett
Xilinx Employee
Xilinx Employee
7,468 Views
Registered: ‎01-03-2008

> I'm stopped dead in my tracks by another bug in the toolchain. what a surprise.....

> ERROR:Xst:2033 - Port I of Input buffer infrastructure_top0/SINGLE_ENDED_CLKS_INST.SYS_CLK_INST is connected to GND
> ERROR:Xst:1847 - Design checking failed

 

This isn't a "bug" in the ISE software, this is an error  in your HDL code.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
eteam00
Professor
Professor
7,459 Views
Registered: ‎07-21-2009

Suggestion for you, xilinx_temp_9099 --

 

This thread is close to 40 posts long, and maybe only 3 of them are interesting topical issues for the general forum population.

 

Why not start a new thread, where your design's technical aspects can be discussed without all the non-technical "distractions".  We can keep this thread around for new postings containing non-technical drama and expressions of snarky wit, so your new thread won't be diluted again.

 

Does this make sense?

 

Merry Christmas !!

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
6,080 Views
Registered: ‎12-18-2010

yes, the "bug" I saw was in my code. I incorrectly saw a xilinx "known issue" with the same error message, but it was for instantiating a specific verilog module IOBUFDS.

 

 

" And that makes you...  half shiny and half droll?


A shiny dtroll?

dtroll?  is that metric eurospeak for demi-droll, as in half-droll?

 

What is the other half of a demi-droll, an ashton-droll?    (used to be a bruce-droll) ?

 

-- Bob "random" Elkind

"

 

You're right Bob, I should stick to the subject matter.

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eteam00
Professor
Professor
6,056 Views
Registered: ‎07-21-2009

You're right Bob, I should stick to the subject matter.

It's your call, just a suggestion:  to open a new - and clear - thread.

It may be a good idea to continue with forum commentary in this thread, and discuss technical issues in a separate thread.

 

Have a good holiday.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
6,046 Views
Registered: ‎12-18-2010

well one good thing is happening - I downloaded ISE 12 last night for linux and have it completely working. Had a lot of trouble with the download cable but I expect things like that with Linux.

 

I used this open source driver:

 

http://rmdir.de/~michael/xilinx/

 

the readme.txt was very helpful in getting it working on my architecture (amd 64 bit gentoo linux kernel 2.6.31 ). If anyone has any problems getting their ISE to work with this configuration let me know. I had to maneuvre udev and install dummy parallel port drivers. but overall it looks good and is a tremendous improvement from my first go-around with ISE/Linux ver 8 back in 2006. Plus being able to edit and implement my designs directly in linux will speed things up tremendously for me. More to come soon.

 

merry christmas.

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6,020 Views
Registered: ‎12-18-2010

I made some more progress over the weekend. I have attached an example that simply copies 5 RXD pins off the PHY and lights up the LED bank accordingly. I tested it with a multicast C++ program on linux and confirmed that the lights come on when I send multicast frames and they shut off when I stop the program. This is a good start.

 

There is of course no IP address, no TCP or network layer. This is just simple UDP that doesn't do anything with the packets. But there is more progress than what is immediately visible: I attached another example app from online that writes "FPGA" to the LCD screen. I learned how to instantiate components so that modules such as the PHY can live in their own file. This will be critical later on so that this project doesn't implode under its own complexity , if and when TCP/IP is attempted.  The hardest part later on will be incorporating the DDR SDRAM, and again, figuring out how to use components is big.

 

For now I'm sticking with VHDL, even though I hear verilog is better for procedural designs. To use these files, simply add them to a blank ISE project. This works great with ISE 12. If you are having major trouble let me know and I'll upload the whole project directory.

 

My next phase is going to be to try parsing udp packets and printing some of the text to the LCD. This will require a generic interface to the LCD to just parse and print a string, so these component instantiations will really help me out. More to come soon.

 

 

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awillen
Mentor
Mentor
6,016 Views
Registered: ‎11-29-2007

Some advice: you used asynchronous resets in your design. When working with FPGAs, you should avoid asynchronous resets except if absolutely necessary. For more information, see Xilinx WP272 Get Smart About Reset: Think Local, Not Global.

If possible, avoid resets alltogether: often it is possible to restrict the reset to control logic and leave the data path without resets.

 

 

Adrian



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If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).
5,962 Views
Registered: ‎12-18-2010

awillen - thank you very much for the design tip. That's the type of subtle bug that would definitely take an experienced designer to know about. versus something obvious in code that I could fix by trial and error. I will definitely incorporate that into my design at some point.

 

I am going to move to the next phase of this design, which will be to use the DDR SDRAM as a buffer off the phy. I want to thank Mike Johnson and his open source pacman program for VHDL on the spartan-3e which he has here

 

http://www.fpgaarcade.com/pac_main.htm

 

This was a great help in seeing a larger-scale design example and how to incorporate different components. of course pacman itself isn't ethernet enabled :) but his code was extremely useful. Unfortunately I didn't have a vga cable to see if the pacman game actually played but I bet it does.

 

Next I will attempt to make the LCD go from just displaying "FPGA" to actually reading 32 bytes from DDR and displaying it. Perhaps after that I will try enabling the rotary knob so you can scroll down the memory.

 

If I can get that to work, the next phase will be getting the PHY to write to memory, essentially dumping the UDP frame to the LCD. I will report back with what i find. Perhaps the pacman author can someday use my ethernet code and incorporate it back into his design to allow you to play pacman against people worldwide via a UDP connection :P

 

 

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5,911 Views
Registered: ‎12-18-2010

hey guys, I just wanted to post an update. I am going to be away from this project for at least a week or 2, so I thought I'd post the progress I've made:

 

* I enabled the DDR ram.At this point, the DDR doesn't actually store PHY data yet, however i confirmed that the write works in the phy.vhd module, and when you write "0x30" / "0x31" manually, you will see '0' or '1' on the lcd. The reason the PHY doesn't work yet is either due to clocking / timing, the characters not being readable, or possibly a logical bug in the way they're being decoded. I am sure I can fix this on my own.

 

* I enabled the LCD and decoded most of the useful characters for it. it currently displays '?' for characters not in the range, since I have no use for the japanese/I-dunno characters on the map. Currently the code writes to the lower row of the LCD since i was tweaking with the address byte. Ultimately I want the rotary knob to control the address of RAM from which the FPGA is reading, and either display the data in the top row with the address in the bottom row, or just dump data to both rows.

 

* I enabled the rotary knob. The idea is this: the knob generates an output signal that is read in by the LCD. The LCD then reads this address from RAM and displays (if it can ) the byte on the panel. This way, I can write a "hello world" multicast UDP packet from the computer, and then scroll past all the packet headers and other junk until I get to the payload, and eventually see "Hello world" on the LCD screen, when I finally get to the payload. The PHY just has a local address that keeps incrementing with every byte that it decodes - it doesn't care what the knob is doing. Currently, the knob sends the signal to the LCD module, but there was a bug and I wasn't sure if the LCD was reading the address, so the LCD module just lights up the LEDS as you turn the knob. Now that I know the LCD is receiving the signal properly, I can resume debugging the DDR ram.

 

* I used a multiplexer to (hopefully) control access to the ram. The PHY is the producer and the LCD is the consumer. There may be a way to do this without a mux by using the HOLD / "ram busy" line, but I was getting the dreaded "multiple drivers for a signal" error. I don't know.

 

The next step is to really understand the LCD clear sequence. At first I just naively tried resetting the whole LCD every time I wanted to referesh it, but obviously that's poor design. i just have to learn how to write the clear byte and get it moving. 

 

Then I need to get the ram scrolling feature to work. I may need a debouncer for the knob, but mostly i want to write serial data to the DDR like "12345" and see it scroll through teh LCD as I turn the knob. Then, I will focus on getting the PHY data decoded properly.

 

 

I'm learning a ton doing this and hopefully this project will be useful to people someday. I will definitely take anyones advice about it if you want to look at the code, but for now I'm just posting to show the progress I'm making. Once I can receive frames, I will work on sending them. Then I will look in to TCP/IP. If everything stays modular, TCP/IP may end up just being a series of state machines with signals that trigger predefined packets. But I've got a long way to go.