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Explorer
Explorer
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Registered: ‎08-07-2013

post-par is able to reflect the FPGA test on board?

Dear Sir,

 

I'm using synplify D-2010.03, ISE 13.1(lin 64) and Spartan 6 XC6SLX150 FGG676 to do a FPGA test for my project in SDI

application.  The flow I'm using is synthesize the verilog codes which contains some DCM generated from coregen, with

a constraint file, top.sdc, on the Synplify, to get a netlist.  And then I use the output netlist file, .edf, with a .ucf file to generate

a programing file or simulation model by ISE.  The test result I saw on the FPGA board seems different from the post-par

simulation.  Why?  Does the constraints not match the board condition?  Or, any other reasons to cause the mismatch?

Thanks.

Another question is about how to keep the design hierarchy in the case I'm running?  KEEP_HIERARCHY in UCF?  It seems doen't work.  Thanks.

 

 

 

Peter Chang

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: post-par is able to reflect the FPGA test on board?

In Vivado, the KEEP_HIERARCHY xdc constraint has limited support. in 2012.4 it can be applied to (design and debug_core) objects. This limits its use to control of hierarchy optimization (flattening) to the full design and Chipscope debug_cores. Due to this limitation, individual hierarchical modules are not controllable using the xdc constraint. In order to control the value of KEEP_HIERARCHY on a module by module basis, please use the rtl version of the attribute. This can be found on page 37 of the Vivado Synthesis Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_4/ug901-vivado-synthesis.pdf

The KEEP_HIERARCHY RTL constraint has different priorities depending on where they are applied. When using the attribute on both a Module declaration and an instantiation of that same module, the instantiation attribute will take precedence and be used by Vivado Synthesis. This can be used to override constraints.



Another limitation of the KEEP_HIERARCHY attribute in Vivado Synthesis is that it is not forward annotated the Implementation tools. This means that the Implementation tools will optimized the hierarchy that has been kept intact during synthesis. Going foward, the "dont_touch" attribute should be used in place of the KEEP_HIERARCHY attribute. The "dont_touch" attribute is forward annotated to the Implementation tools, so the hierarchy will be preserved through Implementation.

Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: post-par is able to reflect the FPGA test on board?

DONT_TOUCH is supported in XDC but KEEP_HIERARCHY and KEEP are not.

Use DONT_TOUCH instread of KEEP_HIERARCHY and KEEP.


. XDC Example: set_property DONT_TOUCH true [get_cells u1]
Thanks and Regards
Balkrishan
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Registered: ‎08-07-2013

Re: post-par is able to reflect the FPGA test on board?

 

Hi Balkris,

 

Do you mean that using Vivado is able to keep the hierarchy?  Or, it is going to be easier to let the post-par simulation be the same as the result on the FPGA board?  A little confused about hte DONT_TOUCH.  In XDC, it can't use KEEP_HIERARCHY?  DONT_TOUCH is supposed to be different from the function of KEEP_HIERARCHY.

 

 

 

Peter Chang

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-14-2012

Re: post-par is able to reflect the FPGA test on board?

Hi Peter

Synplify provides 2 attributes to manage hiearchy, syn_netlist_hierarchy
and syn_hier. The syn_netlist_hierarchy attribute when true maintains
hierarchy in the EDIF netlist. When 0, gives a flattened netlist (though
synthesis may still be maintaining hierarchy). The syn_hier is controls
hierarchy boundaries during synthesis. The syn_hier_netlist does not
affect synthesis, just the output from synthesis. While syn_hier affects
synthesis, and hence, maybe the output EDIF file.

 

Check this AR. This might be helpful.

http://www.xilinx.com/support/answers/17693.htm

 

Regards

Sikta

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Registered: ‎08-07-2013

Re: post-par is able to reflect the FPGA test on board?

Hi Sikta,

 

Thanks for your information.  How to add the attribute into synplify?

Adding it into the .prj?  Thanks.

 

set_option -syn_netlist_hierarchy true

 

 

 

 

 

Peter Chang

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-14-2012

Re: post-par is able to reflect the FPGA test on board?

There should be option in synplify GUI. Otherwise you can provide in RTL also,

 

1

Verilog
-------

module block_A (<port_interface>) /* synthesis syn_hier = "firm" */;

2

VHDL
----

VHDL:
attribute syn_hier: string;
attribute syn_hier of block_A : architecture is "firm";

3

SDC
---

define_attribute {U1} syn_hier {firm}

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Explorer
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Registered: ‎08-07-2013

Re: post-par is able to reflect the FPGA test on board?

Dear Siktap,

 

Thank you.  Let me try.

 

 

Peter

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