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Visitor bobr
Visitor
6,802 Views
Registered: ‎01-21-2011

power up sequencing - glitches during configuration - Spartan3AN

Hi,  I have reached the point where i am thinking about implimentation of a Spartan3AN in my design.  This will be my first FPGA based product.

 

I have a proven design running on a development board, but up until now the develpment board has shielded me from all the low level details and considerations, that can no longer be ignored when designing the production PCB.

 

Therefore i have plenty of questions that need to be ansrwered.

 

I thought i might start with the power supply details -

 

How many different power supplies are involved on the XC3S1400AN? 

What are the power up sequences?

Under what conditions can the power up sequencing be simplified or ignored? 

How do i impliment these sequences in the most economical way on my PCB?

Does Xilinx have reference designs for me to refer to?

 

I have a single XC3S1400AN on my PCB, and i think it will boot from on-chip flash, but i may need to place program code into external ram - does Xilinx have reference designs i can refer to for these functions?

 

Thank you for your help.  :smileyhappy:

Bob

 

 

 

 

 

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15 Replies
Teacher eteam00
Teacher
6,799 Views
Registered: ‎07-21-2009

search first, then post

#1  The first thing that comes to mind is:  you did not bother to search the forum.

 

#2  Here's what you missed by not searching yourself (you get a freebie, this time)

thread

thread

Answer Record

thread

thread

 

These cover the subject, and then some.

 

The simplest solution seems to be:  put an R-C network on the PROG_B pin to ensure that configuration is delayed until all the supplies are 'up'.  The supplies sequence won't matter as long as config is delayed until both FPGA and SPI flash are ready.

 

I have a single XC3S1400AN on my PCB, and i think it will boot from on-chip flash

 

You can be sure that it will boot if you strap the configuration mode pins correctly and program the flash correctly.

 

but i may need to place program code into external ram - does Xilinx have reference designs i can refer to for these functions?

 

Uh oh....  you aren't just new to FPGAs, you're new to designing digital logic boards, right?

 

Do you know which SRAM you want to use?  There are many many SRAMs out there.  For example, go to the DigiKey website and search for SRAM, and see all the options which are available to you.  After you pick one out, you read the datasheet and design an interface in the FPGA for reading and writing the SRAM.

 

Or you can use ROM or PROM instead of SRAM, so that the program code is in place and ready to be fetched at power-on config.

 

Doing this sort of design work without someone experienced to review your work and guide you is...  risky.  Forum posts are not sufficient for this type of guidance and oversight.  I hope you have some help on your project, at least for this one board design.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Instructor
Instructor
6,792 Views
Registered: ‎08-14-2007

Re: Spartan 3AN

Here is a good landing page to find Spartan 3AN Documentation.  I would highly recommend

the Spartan 3 family configuration guide as a starting point.  Also, when designing your own

board you might want to consider using the Spartan 3A and a separate SPI flash chip in the

M25Pxx series for configuration.  It's a bit more flexible in that you can decide how much

flash you want / need for your non-bitstream needs, and it's usually cheaper than the

integrated FPGA/flash.  Note that the 3AN series is a multi-die package - it is not a

flash-based FPGA.  So especially at the larger part sizes you pay a large premium for

that otherwise cheap SPI flash.  And you get pretty much the same part when you order

the Spartan 3A series (other than the "embedded" flash).  Usually this is a trade-off

between board space, price, and design flexibility.

 

As for reference designs, all of the boards and kits listed on the Xilinx site have

schematics in their associated documentation.  So you have quite a few places to

start from.  Just remember that evaluation boards are made for the ultimate flexibility

and therefore tend to have a lot more parts than you need for any one given application.

As an example, many of the eval boards have two or three jumper-selectable forms

of configuration, as well as jumper selectable IO voltages.

 

I think you've got a bit of reading to do before you need to come back for the next

round of questions.

 

Regards,

Gabor

-- Gabor
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Teacher eteam00
Teacher
6,788 Views
Registered: ‎07-21-2009

Re: Spartan 3AN

Ditto to what Gabor wrote.  Have you done any work on a development board?  Which board, and what type of experimentation and design did you do?

 

If you haven't already done so, I strongly recommend purchasing a development board and 'trying out' some of the things you are thinking of designing.  This will help build confidence in your skills and capabilities, as well as prove and test some of your ideas.

 

Don't be in a hurry.  Take your time learning this stuff.  It is much cheaper to learn on a development board than on a custom board design (that is a ginormous understatement, by the way).

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor bobr
Visitor
6,782 Views
Registered: ‎01-21-2011

Re: Spartan 3AN

Thanks for the excellent help and interest Bob, Gabor.

 

I have downloaded and skimmed through the Spartan3 user guide and configuration guide, but i was hoping for the kind of extra insight you have provided.

 

In my experience there is a lot of low level detail that can amounts to an RC here or a pull up there - thankfully. :smileyhappy:

 

I have designed a few digital boards, including a DSP board using a TI DSP, but i thought it was about time i implemented a design in FPGA.  In particular the possibility of increased execution speed of both fixed and floating point DSP functions caught my interest.  I have been developing on the Altium NB3000 development system.  

 

My design includes a 24bit CODEC, some input control buttons, and one or two status output LEDs, and that's it.  With so few peripheral chips, the 'AN' on-chip flash seems attractive.  From what i have seen, external flash also requires a few glue chips in addition, to orchestrate  the configurations process.

 

I have also determined that it just might be possible to place/run the soft-processor code entirely from within the FPGA memory, in which case i could go without external RAM, making the boot sequence even simpler.  My thinking being that keeping my first board as simple as possible may be a good thing.  I still haven't determined if the code will all fit on-board but the main number crunching routine is implemented in hardware - the soft-processor just handles reading/writing ADC/DAC and feeding the data stream in/out of the hardware routine.

 

Comments and suggestions welcome.  I will study the Xilinx development board schematics for more insight.  Thanks for the suggestions.

Bob

 

 

 

 

 

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Teacher eteam00
Teacher
6,776 Views
Registered: ‎07-21-2009

Re: Spartan 3AN

In my experience there is a lot of low level detail that can amounts to an RC here or a pull up there.

 

Reading through the Configuration User Guide is a useful guide, as well as checking out the starter kit development board schematics as an example.

 

From what i have seen, external flash also requires a few glue chips in addition, to orchestrate  the configurations process.

 

No, this is not the case.  An R-C network on the FPGA PROG_B pin should be sufficient for taking care of the needs of SPI flash configuration memory, nothing more.

 

Good luck to you.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Teacher eteam00
Teacher
6,770 Views
Registered: ‎07-21-2009

floating point, you say?

... i thought it was about time i implemented a design in FPGA.  In particular the possibility of increased execution speed of both fixed and floating point DSP functions caught my interest.

 

This finally caught my eye...  implementing a floating point math unit at the gate level is not what I would consider a 'learner' project.  Depending on your performance requirements, floating point is one huge steaming FPGA resource hog (gates and interconnect).

 

If your application depends heavily on high performance floating point math, you can't beat the price vs. performance you get with a true off-the-shelf floating point DSP (e.g. TI, Analog Devices), rather than designing and implementing and verifying your very own FP datapath.

 

Be careful dipping your little pinkie toe into the pond of do-it-yourself floating point.  This has the potential for turning into what is called -- in engineering circles -- a tar baby.

 

You are relatively inexperienced in board design and FPGA design and gate-level system design.  If you are too ambitious in your set goals, there are two increasingly likely results:

 

  • you will never complete the initial prototype, for all the time and attention required to sort out the details

or

 

  • you will give up before you can debug your prototype, because it is too complex and too flawed

Don't let either of these happen to you.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor bobr
Visitor
6,763 Views
Registered: ‎01-21-2011

Re: floating point, you say?

Thanks Bob.  Advice taken. 

 

I know that there is some activity in regards to FP in FPGA devices by the IP guru-masters, but that it has always been problematical.  If i did impliment FP in my design it would definately have to be with off the self 'limited instruction set' IP blocks.  Hopefully one day such a thing will be available royalty free.  A recent article i read predicts that FPGA can eclipse FP DSP FLOP speeds up to ten fold, using new FP IPs.

 

For now i will work with 32bit fixed point.  I guess i could switch to a TI TMS320C6713 FP DSP or equivilent but i felt that an FPGA design would be more versitile and easier to work with - i guess the jury is still out on that...  :smileyhappy:

Bob

 

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Teacher eteam00
Teacher
6,761 Views
Registered: ‎07-21-2009

A long long time ago, in a galaxy far away... FP!!

Keep in mind that a long long time ago, I was the principal designer and architect of the world's fastest commercially available double-precision IEEE-754 FP chip sets, and these were also the largest (die size) production bipolar designs ever (at least at the time of introduction).  The BIT (Bipolar Integrated Technology) B3100/2100 FP chipset helped power (pun intended) the Apollo Domain 10K workstations of the mid-1980s.

 

Now that I've impressed you beyond all human comprehension with my FP expertise, I am highly skeptical of FPGA-based FP cores competing against an ASIC core found in a $10-$30 DSP.

 

Some of the datapaths in a FP unit are gate-intensive, some are interconnect-intensive.  ASIC (custom) design flexibility is essential for performance, and FPGAs of any commercial significance will have too many architectural compromises to compete against true DSPs for FP performance and device power.

 

As for 'royalty-free cores', I am skeptical of their prospects for general appeal.  Ignoring the design tradeoffs for

  • latency
  • bandwidth
  • single vs. double
  • mult vs add/sub
  • full rounding mode and exception support vs. limited support

....  there is so much performance gained or lost in placement and interconnect that effective support for a useful variety of target devices would (in all likelihood) be impractical.

 

And then there's the burden of regression testing for design verification.  Anyone remember the Intel Pentium FDIV bug?  (and those guys were *pros* at the top of their game!)

 

A recent article i read predicts that FPGA can eclipse FP DSP FLOP speeds up to ten fold, using new FP IPs

 

Some day, FPGA devices will be faster.  DSP devices will also be faster.

 

An interesting discussion topic, to be sure, but this is after-dinner conversation rather than ideas which are useful to you in your current design project.

 

Good luck, Bob

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor bobr
Visitor
6,756 Views
Registered: ‎01-21-2011

Re: A long long time ago, in a galaxy far away... FP!!

Thanks for your perspective, Bob.  I won't count on any 10X speed gains then. 

 

Ya, I'm pretty sure my project will do just fine using 32bit fixed point.  The only real reason [that i can think of] that i would prefer FP is the worry of accumulated rounding errors, but with 32bits to work with it probably won't be a problem - that is, i can probably fix any problems such errors create in my design.

Bob

 

 

BTW - i am impressed beyond all human comprehension!

 

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Teacher eteam00
Teacher
4,613 Views
Registered: ‎07-21-2009

Re: A long long time ago, in a galaxy far away... FP!!

The only real reason [that i can think of] that i would prefer FP is the worry of accumulated rounding errors

 

IEEE 754 single precision (32b) FP has a 24-bit mantissa, including the implicit bit and excluding the sign bit.  You may be better off with 32b integer, depending on your algorithms.

 

Are you familiar with the term 'block floating point' ?

 

BTW - i am impressed beyond all human comprehension!

 

You'll get over it, soon enough.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor bobr
Visitor
4,603 Views
Registered: ‎01-21-2011

Re: A long long time ago, in a galaxy far away... FP!!

Thanks.

 

No, i'm not familiar with that term.  Sounds interesting.

 

Another thing i just realized after looking up "Block Floating  Point" is that i am using 'integer' at this point in my FPGA prject, and not really 'fixed point' at all.  It looks like 'fixed point' is also something i need to look into.

 

-Bob

 

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Instructor
Instructor
4,578 Views
Registered: ‎08-14-2007

Re: A long long time ago, in a galaxy far away... FP!!

The only real reason [that i can think of] that i would prefer FP is the worry of accumulated rounding errors

The usual reason to use floating point is that it keeps track of the scaling of numbers

for you (dynamically) so you don't end up tearing your hair out trying to decide which

bits of that multiplier are significant and which can get whacked.  The classic example

of a scaling nightmare is the fixed-point FFT.

 

-- Gabor

-- Gabor
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Teacher rcingham
Teacher
4,571 Views
Registered: ‎09-09-2010

Re: A long long time ago, in a galaxy far away... FP!!

"The classic example of a scaling nightmare is the fixed-point FFT."
I used to find 1 bit every other Radix-2 pass worked well enough most of the time...

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Visitor bobr
Visitor
4,567 Views
Registered: ‎01-21-2011

Re: A long long time ago, in a galaxy far away... FP!!

Thanks Gabor, rcingham,

 

The usual reason to use floating point is that it keeps track of the scaling of numbers

for you (dynamically) so you don't end up tearing your hair out trying to decide which

bits of that multiplier are significant and which can get whacked.  The classic example

of a scaling nightmare is the fixed-point FFT.

 

Do you usually just whack the least significant bits?  In my experience with 'integer' you just divide and let the LSBs slip off the end...  once the number is small enough, the result is zero - the issue i faced using 16 bit integer.  Now i am working with 32 bit integer in this FPGA project.

 

 

 

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Teacher rcingham
Teacher
4,559 Views
Registered: ‎09-09-2010

Re: A long long time ago, in a galaxy far away... FP!!

An example: if you add two 8 bit (unsigned) numbers, then you may need 9 bits to store the result. 202+101 = 303 = (151*2)+1.
Should you round or tuncate? The answer will depend on what algorithms you are performing. Including 'truncation', there are over a dozen forms of rounding.
http://www.diycalculator.com/popup-m-round.shtml

Multiplication is even worse for expanding the bits used: 101*202 = 20402 = (79*256)+178. Here, you probably want to treat the answer as 80.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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